how to constraint a clock when it is slewed from system generator

[mirabelle275]

hi, i simulate a sinewave at 1khz on system generator , the clocking tab is : FPGA clock 20khz and simulink sys period 1/20000 , simulation is ok but when a genrate on hardware (nexys4) the sine wve is 0.2us on osilloscope (it is the case when FPGA work at 100MHZ default clock)

constraint clock is like this :

create_clock -period 50000.000 -name clk [get_ports clk]
set_property BITSTREAM.General.UnconstrainedPins {Allow} [current_design]
set_property PACKAGE_PIN E3 [get_ports clk]
set_property IOSTANDARD E3 [get_ports clk]

what  i must do to ansure the FPGA harware take a 20khz clock in consideration???

[JColvin]

Hi @mirabelle275,

I haven't used Matlab or Simulink in combination with Xilinx's tools, so I'm not certain what you would need to do on that end of things.

As for the create_clock constraint, it does not actually create a clock. It just tells the Vivado software that this particular net should be treated as a clock while it goes through its various synthesis and optimization steps. Pin E3 itself on the Nexys A7 is connected to a 100 MHz oscillator on the board, so you cannot actually change this frequency. You would need to use a clock management tile to be able to create a different clock frequency from the 100 MHz line, though I don't know this would be done in MATLAB; this might be a good resource for you, https://www.mathworks.com/help/hdlcoder/ug/using-multiple-clocks-in-hdl-coder.html, though otherwise you'll probably need to ask on MATLAB Answers, https://www.mathworks.com/matlabcentral/answers/index/?s_tid=gn_mlc_an, to get more specific help.

Thanks,
JColvin