How is the Arty-S7-50 generating a 12 MHz clock on FPGA pin F14?

[Willard]

The Arty-S7 documentation says there is a 12 MHz system clock on FPGA pin F14, but as a posting here pointed out last December, there is no such oscillator. The oscillator position on the board is unpopulated, and the recommendation is to use the DDR clock as a clock source instead of the system clock. Nonetheless, the board file says there is a 12 MHz clock named CLK12MHZ on pin F14, and I have used CLK12MHZ in a simple design and it worked as expected. How is that happening? I can't figure out any clock source.

[JColvin]

Hi @Willard,

The 12 MHz clock is coming from IC10 which is a 12.000 MHz oscillator that also provides the 12 MHz for the FT2322 chip. This particular IC is on the "intentionally left blank" page of the schematic, but you can see the actual IC10 on the underside of the Arty S7 between Pmod JA and Pmod JB. There isn't anything fancy about the connection; if you hold up the board at the right angle, you can see the trace running from IC10 through a couple of resistors and then into F14 on the FPGA itself.

The 100 MHz oscillator that is recommended to be used for the MIG to run DDR based designs is IC3 on the underside of the board between BTN0 and the 6-pin SPI header (J7). That one is visible on page 5 of the Arty S7 schematic, https://digilent.com/reference/_media/reference/programmable-logic/arty-s7/arty_s7_sch-rev_e.pdf.

Let me know if you have any questions.

Thanks,
JColvin