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How do I configure the QSPI IP for controlling a DAC?



Hello, I am using Vivado and Vitis 2020.2 to build a MicroBlaze application for the Arty S7.

My objective is to control a DAC using SPI. I have the QSPI IP configured in standard and running at 390 kHz.


I created an interface port spi_port for the IP and constrained the port to match I/O pins 0, 2, 3, and 4 on the Arty.



Finally, I initialized the XSpi instance, selected the first (and only) slave, and used XSpi_Transfer to MOSI a simple buffer.



When I probe the pins on an oscilloscope, the issue I am seeing is there is no SPI clock on the Arty pin nor data on the MOSI line. Does anyone know where my error is? Thank you

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In the Board tab of the IP, you can select the Board Interface to be Custom, spi, or qspi flash. I had this selected as spi, which I think routed my SPI signals through the J7 SPI header on the Arty S7. The reason I found this was because, when I scoped the SPI header as a test to see if it was activated, I saw the signals from my I/O pins 10-13. In the Arty S7 User Guide, it states that I/O pins 10-13 are tied to the SPI header pins, so I think that I activated the SPI header accidentally, but constrained I/O pins 10-13 which meant that the SPI header was getting my signals from those pins instead.

However, when I create the IP from scratch and select Custom for the Board Interface, the sck_io signal is disabled. How am I supposed to communicate with my SPI peripheral if I can't route a clock to its SCK pin?


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The sck_io signal is unavailable because I had the STARTUP Primitive enabled, which routed the slave clock to STARTUP_IO_cfgmclk_io. As stated in the AXI Quad SPI v3.2 LogiCORE IP Product Guide section Enable STARTUPE2 Primitive Parameter: "This primitive has a dedicated clock pin that can be used to provide the SPI clock to the slave memory" and in Table 2-2: "Free-running clock from on-chip oscillator. Nominally 50 MHz but is not characterized or specified in a data sheet."

Edited by ivansavy
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