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Arty A7 Slave serial mode



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Hi @iyao,

I guess you could? UG470 says that the CCLK is expected to be an input in slave serial mode so that would need to be provided as recommended in the appropriate Xilinx guides. I'm not sure why you would do this though when it seems that Master Serial configuration mode is otherwise the same outside of the CCLK difference (though I guess that also requires cutting a resistor).

Either way, Digilent hasn't done this with our boards so we won't be able to offer much in the way of formal support.


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