iyao Posted October 13, 2021 Share Posted October 13, 2021 Hello, Is it possible to put Arty A7 in slave serial mode by remove JP1 and cutting R188 from GND and jump to VCC? Thanks! Link to comment Share on other sites More sharing options...
0 JColvin Posted October 13, 2021 Share Posted October 13, 2021 Hi @iyao, I guess you could? UG470 says that the CCLK is expected to be an input in slave serial mode so that would need to be provided as recommended in the appropriate Xilinx guides. I'm not sure why you would do this though when it seems that Master Serial configuration mode is otherwise the same outside of the CCLK difference (though I guess that also requires cutting a resistor). Either way, Digilent hasn't done this with our boards so we won't be able to offer much in the way of formal support. Thanks, JColvin Link to comment Share on other sites More sharing options...
Question
iyao
Hello,
Is it possible to put Arty A7 in slave serial mode by remove JP1 and cutting R188 from GND and jump to VCC?
Thanks!
Link to comment
Share on other sites
1 answer to this question
Recommended Posts
Create an account or sign in to comment
You need to be a member in order to leave a comment
Create an account
Sign up for a new account in our community. It's easy!
Register a new accountSign in
Already have an account? Sign in here.
Sign In Now