Makefiles problem in VITIS 2021.1

[Antonio Fasano]

hi, guys,

 

I am feeling frustrated because it is getting more and more difficult to get answers to posts in this Digilent forum. Is something going on that I am not aware of ???

I have a new problem in VITS 2021.1. Makefiles always show errors that I can't get rid of. Picture below. How can we solve it ? 

Thanks

Antonio

[JColvin]

Hi @Antonio Fasano,

A lot of the issue boils down to that those of us at Digilent are not Vivado/Vitis experts either. When we update our own projects and get makefile errors, or replicate a customers question, all we're able to do is some google searches and try different things through trial and error; we don't have any exclusive Xilinx contacts that we can ask questions of anymore than you do.

In terms of what you have posted, where I would start looking first would be the lines mentioned in makefile itself; this is usually available in the Debug folder in the application project. You can also try refreshing BSP sources and making sure the correct hardware platform is referenced, otherwise if I'm being honest, I would also just be searching those errors online and seeing if there is a Xilinx forum thread that is similar. The good news is that makefile errors can be cascading in the sense that they sometimes build off of each other.

Thanks,
JColvin

[Antonio Fasano]

HI,Jon,

 

Yes, Yes - Indeed we don't know what under the hood of Vivado / Vitis and that brings all sorts of problems. I liked best when we had to develop all the VHDL files and nest to one another. That was complex but we had all under control.

They try to automatize everything for the user but when a problem arises, it is never easy to solve, nor there is enough information to guide us in the process of solving it.

I did some more tests and found out that those Makefile errors only appear when I use a certain custom IP that I created. Vivado compiles it without any warning and xsa file is generated without a problem. But in Vitis, the presence of that IP in the project causes the makefile error to pop up.

Would you have any hint to get me going ?

Thanks

Antonio

[Niță Eduard]

Hello @Antonio Fasano,
Can you try to make the following edits on your makefile?
https://support.xilinx.com/s/article/75527?language=en_US
I remember having these issues when moving from SDK to Vitis 2020.1.

However, when moving from Vitis 2020.1 to Vitis 2021.1, we also encountered makefile issues, and these were fixed by making the following change (in addition to the ones from SDK->Vitis):
https://github.com/Digilent/vivado-library/commit/0390827da381069bf0c0a7f46584bcaaadc3ca01#diff-bb9af5d1915da1fbc132ced081325efcd2e63e4804f96890f42e9739677237a4

Hope you find these changes useful.
Best wishes,
Eduard

[Antonio Fasano]

HI, Eduard,

I will reivew those links. I noticed that it has something to do with a custom AXI-4 lite IP I designed.

If I remove it from the design, I get no makefile errors in VITIS.

I don't understand why, as It compiles without problems in Vivado ....

Have you heard of anything like this happening ?

Thanks !!

[AntonioFasano]

Hi, Guys,

Where can I find the makefile ? I can't find the makefile I need to modify !!! Where is it ?

Thanks

[AntonioFasano]

Hi, Guys,

So to fix all those custom-IP related compiling problems in VITIS we need to change the MAKEFILES so it all compliles correctly, right ?  My question is where can we find the makefiles ?  Is it in Vitis or in VIVADO ? What folder ? How can I get to the file to be able to change it ? Thanks

[Riccardo]

Hi Antonio, I have a problem related to makefile now.
The makefile is usually in "Vitis workspace folder"/"name of the project"_system/Debug.

Since some time has passed, did you managed to solve the problem?

 

Thank you 

Riccardo

[Paul_at_PTest]

On 10/18/2021 at 6:04 AM, Niță Eduard said:

Hello @Antonio Fasano,
Can you try to make the following edits on your makefile?
https://support.xilinx.com/s/article/75527?language=en_US
I remember having these issues when moving from SDK to Vitis 2020.1.

However, when moving from Vitis 2020.1 to Vitis 2021.1, we also encountered makefile issues, and these were fixed by making the following change (in addition to the ones from SDK->Vitis):
https://github.com/Digilent/vivado-library/commit/0390827da381069bf0c0a7f46584bcaaadc3ca01#diff-bb9af5d1915da1fbc132ced081325efcd2e63e4804f96890f42e9739677237a4

Hope you find these changes useful.
Best wishes,
Eduard

I had this same problem, I am using Vivado v2023.1 (64-bit) and Vitis IDE v2023.1.0 (64-bit).  My Vivado block diagram worked fine as long as I did not instantiate my custom AXI4Lite IP.  When I instantiated my custom IP, Vivado continued to work fine, producing the bitstream.  I would then export it to Vitis, Update Hardware Specification, and then try to build and I would get the makefile errors, surrounding the makefile for my custom IP.  I then did BOTH of the edits recommended above by Antonio, and this worked for me.