class experiments based on Eclypse Z7 Low Level Zmod ADC DAC Demo

[svip]

Dear All, 
for a class experiment, I am interesting to modify the Eclypse Z7 Low Level Zmod ADC DAC Demo
In order to disconnect the FIR FILTER and make the students insert some custom VHDL modules

the top module of the FIR filter has the following ports

entity Filter_Top_Level is
    Port ( SysClk : in STD_LOGIC;
           sysRst_n : in STD_LOGIC;
           sysInitAdcDone : in STD_LOGIC;
           sysInitDacDone : in STD_LOGIC;
           sysAdcCh1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
           sysDacCh1 : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
           sysDacCh2 : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
         );
end Filter_Top_Level; 

where can i find some additional information about 
sysInitAdcDone  and
sysInitDacDone ?

 

In addition is it possible to know the rates of the ADC and the DAC in the demo?

Thank you all

Luca
 

[JColvin]

Hi @svip,

There is some more about the sysInitAdcDone and the DAC variant in their controller documentation in their respective docs folder on our GitHub: https://github.com/Digilent/vivado-library/tree/master/ip/Zmods. For the Zmod Scope, you'll want to look at section 4.8, and at section 4.6 for the Zmod AWG.

I am working on finding out the rates used; I believe it is 40 MS/s based on the Block Design, but I'll need to double check this with somebody more familiar with the demo.

Let me know if you have any other questions.

Thanks,
JColvin