Hello, I am using Vivado and Vitis 2020.2 to build a MicroBlaze application on an Arty S7 development board. At the moment, I have a 300 MHz clock routed to the UARTLite IP and have selected 921600 as my current baud rate. I've read in two Xilinx articles (https://support.xilinx.com/s/article/35903?language=en_US and https://support.xilinx.com/s/article/14760?language=en_US#:~:text=UART%20Lite%20can%20handle%20baud,rate%20will%20be%208%20MBaud) that I can set the baud rate to the AXI clock frequency divided by 16, though neither give a guide on how to do this. I'd like to set the baud rate to 2 MBaud, which is theoretically allowable for a 100 MHz AXI clock. Is this possible? Thank you
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ivansavy
Hello, I am using Vivado and Vitis 2020.2 to build a MicroBlaze application on an Arty S7 development board. At the moment, I have a 300 MHz clock routed to the UARTLite IP and have selected 921600 as my current baud rate. I've read in two Xilinx articles (https://support.xilinx.com/s/article/35903?language=en_US and https://support.xilinx.com/s/article/14760?language=en_US#:~:text=UART%20Lite%20can%20handle%20baud,rate%20will%20be%208%20MBaud) that I can set the baud rate to the AXI clock frequency divided by 16, though neither give a guide on how to do this. I'd like to set the baud rate to 2 MBaud, which is theoretically allowable for a 100 MHz AXI clock. Is this possible? Thank you
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