Placement problems with DVI to RGB IP

[coldfiremc]

Hi

I'm trying to use the RGB to DVI ip to acquire video, and I'm getting placement errors. if I unpackage IP, I, can't find any "conflictive" setting related to placement, in the sense that there isn't any physical pin reference at all and ISERDES instances look good.
I'm providing the 200mhz ref clock to properly drive input delays and I'm not using any external constraint file. How can I fix or check that there isn't anything wrong?

The board (and related configuration) being used is a nexys Video, and compiling with Vivado 2021.1. The rest of the design has a microblaze, some buttons and leds and the DDR3 memory controller. I'm using the latest IP version from the Digilent IP Repo.

Thanks

 

[elodg]

If you open the synthesized design and navigate to the InputBuffer cell of dvi2rgb you will probably see the input tied to a constant, which causes placement to complain. Check the block design where the TMDS port of IP is tied to. It must go to a top-level port and it has to be constrained to a pin. If you are using board flow and it connects to a board interface, it should be set. Check the top-level wrapper vhd to confirm the top-level ports are generated for the HDMI/DVI input.

[elodg]

It look like you board flow interfaces are not picked up. Dig further.

[elodg]

I will have a look at this as soon as I have some time.

[coldfiremc]

Well, this is not looking good at all

[coldfiremc]

On 10/11/2021 at 6:50 AM, elodg said:

It look like you board flow interfaces are not picked up. Dig further.

After developing a project with this board I noticed that this problem is not only affecting the DVI input IP, but also the clock wizards. Apparently the board file has some inconsistent names. Also the constraints for this IP are a little "Weak" and with a minimum modification, are not applied correctly. Please update the board files. A workaround for this is write constraints manually, but this is not always easy for block designs.

Also there's other problem with rgb to DVI, input frequency is not updated accordingly, so this error appears

[BD 41-927] Following properties on pin /rgb2dvi_0/PixelClk have been updated from connected ip, but BD cell '/rgb2dvi_0' does not accept parameter changes, so they may not be synchronized with cell properties:
    FREQ_HZ = 75000000 
Please resolve any mismatches by directly setting properties on BD cell </rgb2dvi_0> to completely resolve these warnings.

Also incorporating the clock generator inside the ip limit the IP seriously. I think that the integrated clock generator must be discarded to simplify design and allow proper clock settings.
 

Edited January 7, 2022 by coldfiremc

[coldfiremc]

Ok I found something Interesting

Despite the board file has the I/O pins defined for this interface (and an associated IP), Implementation fails because i/o pins are not fixed. This is very strange considering that to assign a pin explicitly is enough to fix the I/O mapping.

This is the error (The ISERDES needs an explicit and fixed mapping)

Here's the "anomaly"

I will check this further, digging in the Board File. Probably it needs a little fix

Greetings

[coldfiremc]

Some News

https://support.xilinx.com/s/feed/0D52E00006wQfP7SAK?language=en_US

There's some little details in the IP and interface definitions. I tweaked a little the Board file also, to fix clocks and not matching of the TMDS interface names. HDMI input has the same problem probably, so it's time to check it

[coldfiremc]

I learned how to edit those xml files. Can I push a new version to the digilent repo?. Can you after that push them to the xilinx board store?

[elodg]

Yes, please create a pull request.

[coldfiremc]

On 2/15/2022 at 11:44 AM, elodg said:

Yes, please create a pull request.

I have 2 pull requests, pls check 🙂
 

[elodg]

Thanks for the contributions. Your fixes seem to work for the Nexys Video in combination with rgb2dvi. I will not be merging them now, but scheduling its extension to the dvi2rgb and all HDMI/DVI Digilent board definition files.