NexysVideo -- [DRC UCIO-1] Unconstrained Logical Port

[Eric888]

I want to add an optical fiber module to NexysVideo, and add the following settings in the Constraint file:
set_property PACKAGE_PIN C9 [get_ports GT_RX_0_N]
set_property PACKAGE_PIN D9 [get_ports GT_RX_0_P]
set_property PACKAGE_PIN C7 [get_ports GT_TX_0_N]
set_property PACKAGE_PIN D7 [get_ports GT_TX_0_P]
The following error occurred after compilation,

[DRC UCIO-1] Unconstrained Logical Port: 2 out of 79 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: GT_TX_0_P, and GT_TX_0_N.

Attach screenshots of NexysVideo and TopFile

[zygot]

So what do you have connected to those pins in your design?

From the Nexys Video Reference Manual: "The gigabit transceiver lane includes a receive pair, a transmit pair, and a reference clock input to the FPGA, all going to MGT bank 216. The transceiver lane is wired to lane 3 (GTPE2_CHANNEL_X0Y7). The reference clock is wired to REFCLK1 of the same bank (GTPE2_COMMON_X0Y1). It is important to keep in mind that bank 216, being the only one available in this FPGA package, is shared between the DisplayPort source and FMC ports. Depending on the exact application, simultaneous usage of the FMC gigabit lane and DisplayPort might not be possible. Regular FMC I/O signals are not affected. "

Generally, transceivers are chosen by specifying GTPE2_CHANNEL locations, in your case GTPE2_CHANNEL_X0Y7. All of the Transceiver IP ask you to specify this. Curiously, the PCIe IP, which uses transceivers, doesn't. In the recent past I was getting the same message trying to implement PCIe for a Kintex board with 4 PCIe lanes and Vivado insisted on using the wrong MGT bank. It took quite a while to figure out how to force Vivado to use the correct MGT resources.

What happens if you comment out all of your transceiver pin location constraints except for this one: set_property PACKAGE_PIN D9 [get_ports GT_RX_0_P]

Vivado bitgen messages can be very confusing. In my experience Vivado doesn't even always accept constraints that it generates.

Artix GTP transceivers have limited clocking capabilities but you should have no problems with 1 GbE.

When connecting transceivers to external boards, as is the case with FMC, I strongly advise reading through UG476 Series7 Transceiver Reference manual. In particular the part about modes with attention to AC coupling.

Edited September 27, 2021 by zygot

[Eric888]

3 hours ago, zygot said:

So what do you have connected to those pins in your design?

From the Nexys Video Reference Manual: "The gigabit transceiver lane includes a receive pair, a transmit pair, and a reference clock input to the FPGA, all going to MGT bank 216. The transceiver lane is wired to lane 3 (GTPE2_CHANNEL_X0Y7). The reference clock is wired to REFCLK1 of the same bank (GTPE2_COMMON_X0Y1). It is important to keep in mind that bank 216, being the only one available in this FPGA package, is shared between the DisplayPort source and FMC ports. Depending on the exact application, simultaneous usage of the FMC gigabit lane and DisplayPort might not be possible. Regular FMC I/O signals are not affected. "

Generally, transceivers are chosen by specifying GTPE2_CHANNEL locations, in your case GTPE2_CHANNEL_X0Y7. All of the Transceiver IP ask you to specify this. Curiously, the PCIe IP, which uses transceivers, doesn't. In the recent past I was getting the same message trying to implement PCIe for a Kintex board with 4 PCIe lanes and Vivado insisted on using the wrong MGT bank. It took quite a while to figure out how to force Vivado to use the correct MGT resources.

What happens if you comment out all of your transceiver pin location constraints except for this one: set_property PACKAGE_PIN D9 [get_ports GT_RX_0_P]

Vivado bitgen messages can be very confusing. In my experience Vivado doesn't even always accept constraints that it generates.

Artix GTP transceivers have limited clocking capabilities but you should have no problems with 1 GbE.

When connecting transceivers to external boards, as is the case with FMC, I strongly advise reading through UG476 Series7 Transceiver Reference manual. In particular the part about modes with attention to AC coupling.

Thank you for the information.

The problem is found.
I use the 7 series FPGAs Transceivers Wizard IP in the project. It may be incorrectly set to cause an error in the synthesis of the IP. It is not a problem with the constraint setting.
After I adjusted the 7 series FPGAs Transceivers Wizard IP settings, it can generate bitstream.

[zygot]

1 hour ago, Eric888 said:

I use the 7 series FPGAs Transceivers Wizard IP in the project.

Then you shouldn't be supplying any transceiver pin location constraints. The IP setup specifies the MGT location and supplies it's own constraints. You should always look at any constraints that Xilinx IP creates to avoid duplicating or creating conflicting constraints in your toplevel constraints file.

I still recommend that you work out ac/dc coupling issues based on the schematics for the Nexys Video and your FMC mezzanine board. Getting a bitstream and obtaining acceptable performance are two different things.

Edited September 27, 2021 by zygot