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Elie Assaf

Pmods AD1 and DA2 use with ZEDBOARD

Question

Hello

I am new to FPGAs, and I'm using Pmods AD1 and DA2 in a control application on ZedBoard, using VIVADO and SDK. Is there any tutorial or hint to know how to start the design and interfacing between ZedBoard and these pmods.

Thanks.

Elie.

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16 answers to this question

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Hi Elie,

You can see some reference projects with AD1 and ZedBoard here. Unfortunately I couldn't find anithing on DA2, but there are some examples for DA1 and DA3 that might help you. You can find them here

Best regards,

Bianca

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Hi,

Adding on to what Bianca provided, here are some reference projects that use the PmodDA2 with some other FPGAs (the Nexys 3 and X-board) available on the the PmodDA2's Resource Center here.

Thanks,
JColvin

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Hi @Sam Bergami,

If you are using HDL(verilog/VHDL) then here is a great project done by @hamster that uses both channels. If you are using the Zynq processor with IP's then here is a link you our github with the PmodAD1 IP. Unfortunately, our IP currently only gives data for one channel. How many channels are you looking to use one or two?   

cheers,

Jon

 

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@jpeyron for the zynq processor link what is the process I would follow to get it functioning? Download the files and then what? I am using Vivado

Edited by Sam Bergami

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Hi @Sam Bergami,

Here is a getting started with Zynq tutorial that might be helpful. The basic process is to create a block design, add the zynq processor, add the IP's that you want to use and run automation. The tutorial walks you though the process. Instead of adding the AXI GPIO add the IP's you want. To have the IP's available in you block design you must download the vivado library here. In vivado you click in the project settings. Click IP and then repository manager and add the full vivado library folder. Make sure you have the board files installed as well(link in the tutorial). There is a way to get hdl code to work with the zynq processor by using the add block feature in Vivado 2016.x. I attached a project that has the hdl code i provided above added this way.

cheers,

Jon

GPIO_add_a_block.zip

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Hi @Sam Bergami,

The compressed project I included above GPIO_add_a_block is a completed project for the PmodAD1. Which has a complete Vivado block design as well as SDK code. This should be a good example for you to add the VHDL code for the PmodDA2 in the design.

cheers,

Jon

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I'm back again @jpeyron.

So I'm having issues with your block design because it is out of date. Any suggestions? I tried recreating it but the AD1 pmod that you use is different from the one in my library.

Which version of Vivado did you use? I am currently using 2016.2

Edited by Sam Bergami

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Hi @Sam Bergami,

There is a PmodAD1 IP core in the vivado library on our github here. The PmodAD1 used in the GPIO_add_a_block zip added above is not the same IP. This PmodAD1 IP was added to the design using the add a block feature in Vivado 2016.x using the vdhl code taken from here and then connecting it to the axi gpio block. I suggested this scenario instead of just using the PmodAD1 from our github so that you had an example of how to add vhdl/Verilog code to your zynq design. We do not have an IP core for the PmodDA2 right now but there is vhdl/verilog code available for the PmodDA2 that could be added to your zynq design using the add a block feature and connecting it to the axi gpio block. On a side not I also suggested this in case you wanted to use both adc channels on the PmodAD1 then you could in the above design. Currently the PmodAD1 only supports one of the adc channels due to the PmodAD1's unique spi configuration. 

thank you,

Jon

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Hi @Sam Bergami,

If you are only wanting to use one of the ADC channels on the PmodAD1 then you can use the PmodAD1 IP core from here. In the zynq processor add another output clock at 50 Mhz and add it to the ext_spi_clk on the PmodAD1 IP core and run automation connections. I have included a completed project with the PmodAD1 only. To add the PmodDA2 to this design you will need to use the add a block feature using VHDL/Verilog code along with the axi gpio block as i have discussed above.

cheers,

Jon

 

PmodAD1.zip

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