In asic design, I just put a request into our libary person to build a RAM the size I need, and get a module back with some behavioral code underneath. Not sure how it works in zedboard/vivado.
I need a 4k x 16bit ram. and a much smaller 16 deep x 32bit wide ram. i coded them for a read port and a write port, but I could combine into one port if that helps. It needs to run at 100mhz.
the 16x32 might be able to be built with flops. But I doubt the 4k block can be done in flops.
do you just try to synthesize to see if flops will work?
reg [31:0] smallram [15:0];
reg [15:0] bigram [4095:0];
Are there some modules that let me instantiate the underlying ram cells in the zedboard?
I tried googling for zedboard block ram and found somethign that generates ram blocks with axi interfaces? That was more complicated than I needed. I was hoping for a paramaterized module that lets me specify width and depth? and a straightforward write/read bus, not AXI interface. I don't even know what to google. do you call that a block ram in vivado/zedboard speak?
If this is already answered/explained somewhere else, just point me to it and I'll go there.
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skinnypanda
In asic design, I just put a request into our libary person to build a RAM the size I need, and get a module back with some behavioral code underneath. Not sure how it works in zedboard/vivado.
I need a 4k x 16bit ram. and a much smaller 16 deep x 32bit wide ram. i coded them for a read port and a write port, but I could combine into one port if that helps. It needs to run at 100mhz.
the 16x32 might be able to be built with flops. But I doubt the 4k block can be done in flops.
do you just try to synthesize to see if flops will work?
reg [31:0] smallram [15:0];
reg [15:0] bigram [4095:0];
Are there some modules that let me instantiate the underlying ram cells in the zedboard?
I tried googling for zedboard block ram and found somethign that generates ram blocks with axi interfaces? That was more complicated than I needed. I was hoping for a paramaterized module that lets me specify width and depth? and a straightforward write/read bus, not AXI interface. I don't even know what to google. do you call that a block ram in vivado/zedboard speak?
If this is already answered/explained somewhere else, just point me to it and I'll go there.
thanks
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