• 0

NetFPGA-1G-CML QDRII+ interface


Question

8 answers to this question

Recommended Posts

  • 0

Hi @zygot,

I asked one of our design engineers about this and I think it's actually just a mismatch in the schematic symbol/labeling? The confusing pin configurations table in the CY7C2263kV18 (datasheet link) only lists 19 pins as "A" which are defined as the input synchronous address-inputs. How one would determine which A<x> pin goes to which pin on the FBGA, I am not sure.

As for why the schematic lists 20 of these A<x> pins rather than only 19 since there are only 19 on this chip, I do not know. But the functionality of the QDRII+ should not be affected.

Thanks,
JColvin

Link to post
Share on other sites
  • 0

I'm really hoping that the schematics presented to customers aren't documentation recreations of the actual schematic. But the schematic clearly shows the memory device A5 pin as unconnected to anything. If the schematic that I'm looking at is the one used to layout the board then we [ the users ] have a problem. I don't understand how that wouldn't alter the device functionality. Suspiciously, the open source repository has nothing supporting the QDRII+ device so this isn't encouraging.

I've read the device documentation and the Xilinx IP documentation and nothing in any of those documents suggest doing something like this, even for the MiG core generator.

Edited by zygot
Link to post
Share on other sites
  • 0

It's disappointing that the QDRII+ memory was botched and is unusable.

I've tried to find a Mig project for the DDR... or any indication that anyone has ever used it. I haven't.

When you do the board test, does that include the DDR? If so could you make available the MiG project settings? Is is possible to obtain test sources?

The board would be very handicapped without any external memory.

Link to post
Share on other sites
  • 0

The NetFPGA-1D-CMT user reference manual states that it supports 1600 MT/s, or 1600 Mb/s per pin. This is consistent with the datasheet information for the -1 part for a 4:1 controller. The maximum BUFIO clock rate, according to the datasheet is 710 MHz, so I'm not sure how one gets an 800 MHz clock to the IOBs.

Does Digilent actually test the DDR on the boards to verify its claimed performance?

Link to post
Share on other sites
  • 0
On 9/3/2021 at 12:55 PM, JColvin said:

I do not know. But the functionality of the QDRII+ should not be affected.

Well, if you advertise a product capability then anyone buying the product would expect that you are testing and verifying advertised claims. I suspect that the only thing being tested, if anything is, would be the Ethernet ports and possibly the PCIe interface. But it's not hard to prove that the published schematic is different than the actual board design schematic and that the QDRII+ memory works as advertised. Just make available the test code so that users can perform the test for themselves.

If the advertised claims for this board are incorrect or untested then Digilent needs to do something about that.

Edited by zygot
Link to post
Share on other sites
  • 0

Hi @zygot,

I don't have any helpful comments regarding on the NetFPGA repository not offering QDRII+; that repository was/is created and maintained by the NetFPGA group. The folks at CMLAB (support at cmlab dot biz) may have some more helpful details on existing design implementations, but I do not know what they have available.

I otherwise got these more other details from another design engineer regarding the schematic for the QDRII:

Quote

I have 0 experience with QDR-II+. From what I dug up just now:

Ball C6 is NC in CY7C2263KV18, so the schematic symbol is incorrect, but used correctly in the schematic. Somebody else did the 1G, I am not sure who created the schematic symbol.

QDR-II+ chips with Two-Word Burst Architecture use C6 for an address. The schematic symbol can accommodate both, but it is not done in a self-documenting way.

I know all of our boards are tested at the factory for functionality for each of the on-board components, though I know nothing about the 1G CML. I'll ask to see what was done for the QDRII+ and the DDR3.

Thanks,
JColvin

Link to post
Share on other sites
  • 0

@JColvin, Thanks for the information.

I'm trying to see if the DDR works. It certainly doesn't do 1600 MT/s as 800 MHz is beyond the range of the -1 part clocking specifications. Oddly, Vivado will complain about an 800 MHz clock but will create a bitstream if you add a CLOCK_DEDICATED_ROUTE_BACKBONE constraint. Unfortunately, this is of little use as timing is so bad as to make the analysis useless.  I haven't run into any information about anyone using the DDR on this board.

I have no explanation for why the datasheet claims a 1600 Mbps maximum DDR rate for memory applications when the device isn't capable of anything close to supporting an 800 MHz internal clock for the MMCM, PLL, or clock buffers.  I suppose that I can live with a slower DDR performance; assuming that I can get it to work.

 

Link to post
Share on other sites
  • 0

I believe that I've managed to get the DDR3 memory working using Vivado 2020.2. It has to be a 2:1 clock ratio, 800 MT/s design. It's a shame that a DDR3 part with an 8-bit DQ bus was chosen for a board with four 1 GbE ports; but at least some local storage is available.

Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now