Best way to match falling/low level IRQs to Zynq's rising/high level requirement

[edge30]

Zynq PL-PS IRQ's are predefined as acting at rising edge/high level.

When interfacing external devices, most commercial devices generate falling edge/low level.

I've been inverting the polarities using verilog code, but it seems a little odd to me. I wonder if there's already a 'proper' way to deal with this situation, maybe I'm missing something since I don't see anybody mentioning this.

Any advise?

Edited August 22, 2021 by edge30

[zygot]

Have you read the ug585-ZYNQ-7000-TRM GPIO section; specifically 14.2.4?

The ZYNQ interrupt complex is quite complicated and the documentation isn't always very clear.

But really, the point of the PL is to let the designer create the external interface to suit just about any hardware, that best suits the designer's needs, so I don't think that there is a 'proper' way. Personally, if it doesn't consume too many resources I'd rather simplify my software development at the expense if a few lines of HDL code. I wouldn't think that there's a 'proper' way to handle your issue. here's a lot of ways to do most anything. Usually, there's only one optimal way, a few easy ways, a lot of hard and complicated ways, and an almost infinite number of wrong ways to solve a problem... and of course it all depends on your project requirements and constraints.

Edited August 23, 2021 by zygot

[JColvin]

Hi @edge30,

@zygot is correct that UG585 is the best resource for details on the interrupt, though I also recommend looking at section 7 (in addition the previously mentioned GPIO interrupts functionality) as most of the PL-PS interrupts are Serial Peripheral Interrupts. Reading through the documentation though and based on this Xilinx Forum thread, I don't believe there is a way to change the sensitivity level to low or falling edge. Table 7-4 makes it seem like Rising Edge/High level interrupt sensitivities are the only option for Serial Peripheral Interrupts, though the 4 Private Peripheral Interrupts for the CPU cores might be at an Active Low Level (Table 7-3), though they are not configurable.

Regardless, I also think using a few lines of HDL will be your best option as I don't think there's a way to do it through any register settings (though I haven't dived into to the nitty gritty of the available documentation).

Thanks,
JColvin