The Genesys Zu board comes with DDR4 RAM which I have tried to use integrate with DMA but without any luck. My end goal is to send binary data from the PL fabric into the DDR4 RAM independent of the APU. May someone provide me with a list of things that need to be changed for the AXI DMA IP Core and the Zynq UltraScale+ MPSoC in order to accomplish this?
I especially need instructions on how to configure the SoC for DMA because there is clear documentation on the AXI DMA IP Core but not the SoC for DMA purposes. I have already set up the AXI DMA register space correctly, but I do not know the SoC's AXI ports well. They only show up on Vivado Re-customize IP as highly abstracted out ports. I am guessing the main issue is not having the right high performance AXI interfaces enabled on the SoC.
Edit 1: I came back to clarify that I am running bare metal C programs, if it matters.
Question
QI109
The Genesys Zu board comes with DDR4 RAM which I have tried to use integrate with DMA but without any luck. My end goal is to send binary data from the PL fabric into the DDR4 RAM independent of the APU. May someone provide me with a list of things that need to be changed for the AXI DMA IP Core and the Zynq UltraScale+ MPSoC in order to accomplish this?
I especially need instructions on how to configure the SoC for DMA because there is clear documentation on the AXI DMA IP Core but not the SoC for DMA purposes. I have already set up the AXI DMA register space correctly, but I do not know the SoC's AXI ports well. They only show up on Vivado Re-customize IP as highly abstracted out ports. I am guessing the main issue is not having the right high performance AXI interfaces enabled on the SoC.
Edit 1: I came back to clarify that I am running bare metal C programs, if it matters.
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