Cora Z7 10 Board Gerber Files

[Todd Cooper]

Hello,

I have a Cora Z7 10 board and would like to view the routing of some of the signals on the inner layers of the PCB to determine if they can be used for LVDS.  Can you please supply the PCB layout Gerber files or equivalent?

Thanks

[JColvin]

Hi @Todd Cooper,

If I'm not mistaken, you'll be limited at a hardware level because Xilinx's Zynq 7010 SoCs only support LVDS at 2.5 V, but the FPGA banks with the differentially paired pins are powered at 3.3 V as per pages 8 and 9 of the Cora Z7-10 schematic, https://s3-us-west-2.amazonaws.com/digilent/resources/programmable-logic/cora-z7/Cora+Z7_sch-public.pdf. While you could specify in the .xdc file that certain pins are operating at 2.5 V LVDS rather than 3.3 V CMOS, you would be restricted to the LVDS details in DS187 and UG471.

This other Forum thread has some additional details as well:

Thanks,
JColvin

[Todd Cooper]

Hi JColvin,

Yes, all of the PL IO pin bank voltages appear to be set to 3.3V and it looks like the Zynq 7010 disables the LVDS outputs if the IO pin bank voltage is >2.85V please see attachment.  From the Cora Z7 schematic, the supply voltage for the LVDS IO pin banks 34 and 35 come from the Buck 3 Output of IC15 which is a Dialog DA9062 PMIC.  This PMIC's output voltage is programmable and it's programming ports can be accessed from unpopulated connector J14.  Buck 3 output is programmed initially to be 3.3V. Is it possible to re-program the DA9062 Buck 3 output to 2.5V to enable LVDS drivers on the Zynq 7010?  If so, please let me know how to do this.  Thanks

[zygot]

It's a shame about the lack of LVDS capability or usability on Digilent's FPGA boards.

If you need balanced connectivity to an external board you can usually design a simple PMOD compatible interface board using discrete parts. This might be preferable as you have a wider selection of differential logic types to choose from. Some receivers have internal termination which is ideal when it should be as close to the receiver inputs as possible. It's a shame that PMODs only support 8 IO pins with no guarantee that any of the will be clock capable FPGA pins. Furthermore, even if you want to use a high speed PMOD that has reasonably length matched pair pins, it's unlikely that matching of all pairs will be very good.

Modifying your board's power supply isn't recommended as GPIO connectors likely have their pins tied to IO banks which also have peripheral interfaces that need 3.3V tied to it, and you might not want to lose functionality. Of course you can check the schematic to see what's connected to an IO bank. Digilent's schematics of course have blank pages.

The best option is to find a board that supports LVDS connectivity, as you need to implement it, by design. The low end Xilinx FPGA device don't have HP IO banks or internal termination options.

Edited August 21, 2021 by zygot