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What models/sample rates are the ZMODS included with the eclypse z7?


dmeads_10

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Well, what sample rates do you want?

There is no set of available sample rates for the ADC and DAC devices on these SYZYGY compatible pods. However the pods include more than just a converter. There's also analog circuitry included which make them good general purpose add-on boards. This also implies that the analog support circuitry is optimized to work near the limits of the converter upper sampling range. This doesn't mean that you have to use the maximum Fs for the pods, but you have to understand the consequences for choosing an arbitrary Fs. Digilent has provided very good documentation about the designs of both. The converter vendors also supply a datasheet and good applications information.

If you do ADC sampling at say, 100 MHz, that doesn't mean that your system has to work with 100 MHz samples. You can process those 100 MHz samples to achieve an almost arbitrary sample rate using decimation and interpolation.

The Eclypse-Z7 has a number of design flaws as a mixed signal FPGA platform. The most glaring is the lack of external clock inputs and outputs limiting its usefulness. This isn't because of any deficiency in the SYZYGY specification, though the standard pod sizes don't leave a lot of room for extra connectors. Still, allowing for an external synchronization clock on the pods might have been an option.

This doesn't mean that there aren't good uses for the Eclypse-Z7 or ZMODS.

I view these boards as suitable for developers with advanced skills in HDLs, AXI busses, and perhaps Linux development. At the minimum anyone considering using them should be able to understand the requirements of the projects they intend to develop for them and be able to complete the HDL and software components from scratch. That's just my opinion, based on experience with them.

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Okay, I was referring to the specific model number. When you look at the ZMOD ADC 1410 there are three different models, each with a different max sample frequency, I am just wondering which one is included when you purchase the board with the ADC option. 

Thanks for the feedback tho, I am planning to use it for some intermediate level DSP exploration, along with some SDR stuff and making a hobbyist service monitor for my handheld radio. any option of the ADC would be fine for my projects I am just wondering which one is included when you buy it. 

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Sampling rate isn't specifically an FPGA issue. Having external clock inputs and outputs isn't just about clock synchronization.

Imagine that you a system with one of the components an FPGA based board with ADC and DAC capability. There are a number of reasons why you might need coherent system wide sampling. If your ADC is converting a signal generated by a system DAC you might have phasing requirements. An external clock input allows your FPGA platform to have an Fs that is more accurate or steady over time or environmental fluctuations than what the board vendor can provide for a reasonable cost. Sytem Fs might not be constant over the measurement interval. Fs might not originate on one FPGA board. You might not have only one FPGA based board with converters in a system. Clocking is the very basic place where systems engineering starts.

As a purely educational platform not having external clocking access might be fine, for a limited set of purposes. As a working platform this might be a huge problem. A couple of SMA connectors certainly isn't a prohibitive additive cost for something that the Eclypse-Z7 aspires to be. Not all customers of low cost FPGA platforms have simple educational projects in mind.

The Eclypse-Z7 is Digilent's foray into SYZYGY compatibility. SYZYGY is a standard that let's Xilinx customers use the Series 7 IO to all of its capabilities with relatively low cost and high performance headers. Customers can use pods available in the market place or create their own custom pods within a tight budget ( not that these connectors are trivial to lay out using free PCB tools or for low layer count board design ). Digilent is free to pursue whatever market strategy they choose to. FPGA board users are a diverse group and just want to be able to use FPGA device features to accomplish a task. I don't speak for Digilent or any other vendor. I speak on behalf of their customers and users. As a user I don't want to buy a platform that is designed to limit its usefulness, especially when there isn't a cost or technical justification for doing so.


Edited by zygot
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Well there are FMC mezzanine cards with mixed-signal (ADC/DAC) interfaces that provide for connecting a system reference clock via an suitable connector. These tend to be very expensive. So the Nexys Video or Genesy2 boards might be a suitable platform. Not providing the possibility of using an external reference clock is a major design flaw for any platform that claims to be a mixed-signal platform in my opinion. I don't believe that Digilent's SYZYGY carrier boards were designed wit customer needs in mind.

Before Digilent came out with the Eclypse-Z7 and ZMODs Intel based boards with an HMSC connector were the only viable FPGA platforms around for doing mixed-signal applications at a price point for hobbyists. Terasic sells suitable hardware, though the cost of Cyclone V or Cyclone IV boards have become pretty burdensome ( twice what they were when introduced )

What you have to look out for when considering selecting hardware is the details. For instance Terasic's DCC has 2 ADC and DAC channels that exceed any of the ZMOD Fs and an SMA connector that accepts and external reference clock. What's less obvious is that the ADCs and DACs are connected through wide-band transformers, so you lose DC and low frequency response.

The nice thing about the so called ZMODs is that they were designed for Digilent's transition into an instrument company. So, they provide really nice flexibility for most general purpose ADC/DAC applications.

If I have my way all FPGA development boards would have at least on SMA clock_in and one DMA clock_out. Rarely, do I get my way... Edited by zygot
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