Question

I'm using Nexys A7-100T developmennt board.

I'm having issues getting Pmod I2S2 to work.

This is my test design:

image.png.c6b4fb000f6ef22109c0705b5aa45600.png

The clocking wizard creates a 11.289MHz master clock.

The tranceiver module I'm using can be found here: https://forum.digikey.com/t/i2s-pmod-quick-start-vhdl/13065. It seems to be generating the serial and ws (word select) clocks properly.

The problem is that I'm not getting any signal from the ADC. sdout pin stays high no matter what. Even if LINE IN was floating, I would expect zeros between left and right channel data. Is the Pmod faulty or am I missing something?

image.png.8c5d6841118c82a3c786a47204f01711.png

The pinout looks fine too

image.png.8488921642ec48657aafdf84e162ac22.png

I connected headphones to the output and don't hear anything. Not even static.

Please help me out on this I'll highly appreciate.

Edited by Jan Kager
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@Jan Kager

It looks like the constraints for the top and bottom row of the Pmod port are swapped. I don't have a Pmod I2S2 to test with at the moment, but was able to get the transceiver core running with your constraints and a Pmod I2S (which uses the same CS4344 chip used in the I2S2's line-out) connected to the bottom row of port JA. I've attached the Verilog module I used to generate the audio output data for testing, as well as a screenshot of the block design.

Please also check that your MST/SLV jumper is in the SLV position, since the transceiver core generates the clocks for the line-in chip, rather than taking them as input.

Thanks,

Arthur

 

module audio_test_pattern(
    input clk, // 11.29 MHz mclk
    input lrck_in, // 44.1 kHz lrck
    output [23:0] count_out
);
    reg store;
    wire enable;
    [email protected](posedge clk) begin
        store <= lrck_in;
    end
    assign enable = store & ~lrck_in;
    
    reg [23:0] count = 0;
    assign count_out = count;
    [email protected](posedge clk) begin
        if (enable) begin
            count <= count + 24'd100000; // the counter rolls over at ~262 Hz
        end
    end
endmodule

image.png.bd7f20702eebe81dcfa65c5753e44853.png

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Oh god! Of course. I can't believe I overlooked something this simple. Thank you for your help. I'm receiving a signal now, but I still can't hear anything. I can see changes on the ad_sdout pin, so I think it reacts to the microphone, but I can't be sure until I connect it to a speaker. Are there any tests I could do to determine the issue?

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The voltage provided by a microphone tends to be quite low. You could potentially amplify the signal before it reaches the I2S2, multiply it up in the FPGA (resulting in a poor quality signal, since you are only effectively using the lowest couple of bits), or try out your project with a cable connected to a computer's audio out. I'd recommend the latter if you happen to have a 3.5mm-3.5mm cable lying around.

Getting a bunch of samples dumped into block RAM and then potentially out over UART or into the ILA in a burst could be a good way of looking at more than just one sample at a time. Could potentially also wire something up to look for the minimum and maximum values received in the incoming data.

Thanks,

Arthur

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