RGB2DVI, DVI2RGB support for Spartan 7

[ajaykumar]

Hi,

Are the RGB2DVI and DVI2RGB IPs not supported in Spartan 7 for lack of supported IOs or lack of supported boards from digilent?

If it is due to lack of supported boards, can we use the IP targeting a spartan device by add spartan to list of supported devices in IP file?

Thanks ,

Ajay

[JColvin]

Hi @ajaykumar,

It's for the lack of appropriate IO interfaces on Digilent's two Spartan 7 based boards (Arty S7 and Cmod S7).

If you have your own Spartan 7 board that has built in IO interfaces, then you should be able to edit the component.xml file to add the lines

<xilinx:family xilinx:lifeCycle="Pre-Production">spartan7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">spartan7l</xilinx:family>

to the <xilinx:supportedFamilies> section which is around line 733.

I haven't gotten to try this yet (and don't have a board where I could actually try a design), but I believe it should work. The caveat with this approach is that you could run into some IP versioning issues, but those can be mitigated.

Let me know if you have any questions.

Thanks,
JColvin

[ajaykumar]

Hi @JColvin

Thank you very much for the details. I have edited the lines and created a Vivado project with these IPs as input and output of the pipeline targeting a Spartan device (xc7s6cpga196-1). I have not faced any issues with respect to versioning. I have also synthesized it, without IO mapping and it went well. 

I will try that as well and get back to you with synth and implementation results. I too do not have a board as of now to test it on hardware. Looking for options. 

Meanwhile, can you clarify on this->  The Arty S7 and Cmod S7 use CSG324 and CSG225 packages respectively and both of them have a decent number of IOs 100 / 150. When you mentioned lack of appropriate IO interfaces, is it that all these IOs were used for other purpose as the intent of the board design is different or is it that the IOs in these parts are not compatible with digilent TMDS IO type?

Thanks and Regards,

Ajay

[JColvin]

Hi @ajaykumar,

All of the pins were routed out for other purposes for the board design; you can see the pin assignments on the schematics for the Cmod S7 and the Cmod A7 (available on their Resource Centers, Cmod A7, Cmod S7) and that nearly all of the pins for each board have been assigned as per Xilinx's UG475. Digilent just didn't

In terms of if the IO pins on different Xilinx Artix and Spartan architectures and package layouts are compatible with the Xilinx TMDS typing, the best place to learn these answers would be Xilinx's DS180 and UG471. On a surface level though (I haven't done any detailed research), the pins on the Arty S7 and Cmod S7 are physically compatible. I know that the Cmod A7 does not have any video based connectors on it, but it can be used for video purposes like this talented forum user did:

Thanks,
JColvin

[ajaykumar]

Hi @JColvin

Thank you for the details. This clarifies most of the things for me. What I am going to do now is pick a spartan 7 break out board, and build a test board with HDMI IO ports. Will update you with the results.

Thanks and Regards

Ajay

[ajaykumar]

Hi @JColvin

In continuation to the effort, I was validating an architecture which is intended to work like a display broadcast solution. I take a DVI input into the FPGA using DVI2RGB IP. I then use this RGB output to multiple RGB to DVI IPs, with pixel clock and serial clock appropriately taken care.

As a precursor to this, I have tried testing an input - output combination with this IP. I have taken the Zybo Z7 HDMI design , and connected the RGB output from DVI 2 RGB IP directly to RGB 2 DVI IP, with pixel clock and serial clock still coming from the dynamic clock wizard.

I have ensured that input resolution and output resolution are specified to be same. In addition to this I have also tried a simple fresh design with just the 2 IPs connected in similar fashion, clocks taken care appropriately.

I could not see any output on the display for both the cases. Is the RGB output from DVI2RGB not sufficient as an input to RGB2DVI IP? Or am I missing out anything here?

Thanks and Regards

Ajay