HDMI out issues with Arty Z7-20

[Alessandro Reineri]

Hello everyone! I am a FPGA rookie programmer and I have recently bought an Arty Z7-20 board for a university project. I intended to write a simple RTL HDMI transmitter with TMDS encoder. However, I found difficulties in implementing the design on the target FPGA, although all simulations I run on Vivado stated the correct top-module behavior. I also tried to implement the Diglilent official HDMI out demo for Z7-20 package but it did not work neither. Any suggestions ? I am sharing all my project's files attached to this post. Thanks in advance to everyone which will provide any help.

P.S. : the project's top-level module is "Video_Generator.v";

Debouncer.v TickCounter.v TMDS_encoder_HDMI.v Video_Generator.v Video_Generator.xdc ClockGenPar.v

[JColvin]

Hi @Alessandro Reineri,

What version of Vivado are you using and which particular release did you use for the Arty Z7-20 demo?

Thanks,
JColvin