Operating ZMOD ADC 1410 at lower sampling rate.

[su_21]

Hello Friends,

I have Eclypse - Z7 and Zmod ADC 1410, my application only requires to capture 4-5 different types of signals and stores in it DDR, further transfer the same data to host PC. There are some signals for which I have to operate the ADC at lower sampling rate(compared to 100 MSPS) and I'm thinking to do that with Zmod only. However, I have gone through the Low level IP provided by Digilent and also through the AD9648 datasheet, and I found that ADC9648 has internal clock divider. I'm thinking of changing the integer value of clock divider (using IP) or provide low clock signal to ADC(existing design provides 400 MHz clock). I am not sure about this and I haven't done anything on Eclypse - Z7 yet, anyone have done this before or suggestions for the same, I request you to provide me the information on the same.

[attila]

Hi @su_21

Leave the 100/400MHz ADC sampling frequency and skip the unneeded samples to reduce to the required rate, or perform averaging/filtering.

Changing the ADC freq would affect the vertical range (and offset), would require new calibration.
The 4x input clock is useful to reduce the jitter, to have better accuracy.