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Interface ADS4225EVM FMC LPC Board


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Hi

I have to interface an ADC for a project, and this ADC(ADS4225) fits the requirements. I'm planning to buy the development board and the needed adapter to connect it to the FMC port of a Nexys Video. However, I never interfaced a high speed DDR LVDS device before, and this device (and all of its class) need some signal adjustments to get the data links properly aligned.

Can I get some guidance to implement input delays and DDR clock calibration?

Thanks

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I've spent many an hour over the years looking into connecting various converter EVMs to Digilent FPGA boards and I can tell you that this is tricky and requires a lot of work, even if the EVM has a compatible FMC connector.

The first place, before you start thinking about timing constraints, is to understand the advanced IO features of the FPGA you will be using. This means reading the Series7 Select IO and clocking reference manuals very carefully. There are rules and limitations to understand that aren't obvious to someone without prior experience. Xilinx offers a number of application notes with sources that can be informative, but you need to know what questions to ask as you go over them. These will help you understand the mechanics of how to get LVDS working. 14x LVDS isn't the same as 7x LVDS.

Since you already have the FPGA platform decided on the easiest path would be to use an ADC EVM that has an LPC FMC connector and comes with demonstration support. Since you didn't mention your converter requirements, I won't mention the subject except to say that not all converters are appropriate for all applications, especially those aimed at comms. Be aware that a lot of vendors use the connector that the FMC standard uses. This doesn't necessarily mean that they are compatible with Vita57 or any particular standard... just that the connector was used. Even if the EVM is Vita57 compatible there are still potential issues for LVDS greater than 8x data rates. You need to confirm not only connectivity of signals between the EVM ADC and the FPGA but that the data and clocks make it to the right IO bank according to the rules for your device. ADI has a number of EVMs that come with demonstration projects to work with specific FPGA platforms. ADI has better FPGA support than other vendors. It's typical, especially for high speed converter devices, for vendors to require that EVMs be used with another expensive control board. Understand that most converter EVMs are designed for confirming specifications only, not for use in a real world project application. The vendors don't want to be in competition with their customers for obvious reasons.

If you are going to select an ADC EVM without an FMC connector then you have to figure out how to connect the two boards. Working with even the LPC FMC connector isn't trivial. Expect to use at least 4 signal layers on any adapter PCB you might design. Differential routing for very high speed signals requires more than just matched _n and _p length matching. You likely need to implement proper differential signal routing. If you use wires or cables then you need twisted pair cabling. Even if you find a cheap way to do this routing signals to a custom cable assembly header isn't trivial. Be aware that converter EMVs may be set up is a way that isn't compatible with your application needs.

Assuming that you've worked out all of the connectivity issues you should read everything that Xilinx documentation has to offer concerning timing closure and constraints. The material tends to be out of date with respect to the tool versions. The main GUI page of Vivado offers templates for all manner of constraint syntax if you plan on writing your own constraints; that's how I prefer to do things. In my experience though the templates aren't necessarily that helpful as I've followed them on many occasions only to have the tools reject the syntax, and constraint, without sufficient guidance. Usually though you can do enough googling to figure out how to correct the syntax to work with your VIvado version. You can also use the Vivado TCL console to get help with just about any detail including syntax. Personally, I don't I don't find the constraints wizard to be all that helpful.

The real head-scratchers come when you get into the details.

My main point here is that figuring out what the vital details are and working out a solution often can't be worked out after selecting hardware, so get it right before you commit to hardware. All of the observations above assume that you've already worked out the timing according to the AC specifications for your FPGA device.

Edited by zygot
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