I've installed the latest Vivado 2021.1 suite and try to compile an old blinky design in VHDL, here below the source code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity blinky is
-- Port ( );
port (
sysclk : in std_logic;
led : buffer std_logic_vector (1 downto 0)
);
end blinky;
architecture Behavioral of blinky is
constant max_count : natural := 48000000;
signal Rst : std_logic;
begin
Rst <= '0';
-- 0 to max_count counter
ctr_led : process(sysclk, Rst)
variable count : natural range 0 to max_count;
begin
if Rst = '1' then
count := 0;
led(0) <= '1';
elsif rising_edge(sysclk) then
if count < max_count/2 then
count := count + 1;
led(0) <= '1';
elsif count < max_count then
led(0) <= '0';
count := count + 1;
else
led(0) <= '1';
count := 0;
end if;
end if;
end process ctr_led;
end Behavioral;
on the Digilent Cmod-A7-Master.xdc file I've uncommented following lines (clock and led):
## This file is a general .xdc for the CmodA7 rev. B
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## 12 MHz Clock Signal
set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {sysclk}];
## LEDs
set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L12N_T1_MRCC_16 Sch=led[1]
set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L13P_T2_MRCC_16 Sch=led[2]
## RGB LED
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L14N_T2_SRCC_16 Sch=led0_b
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L13N_T2_MRCC_16 Sch=led0_g
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L14P_T2_SRCC_16 Sch=led0_r
Synthesis give no errors but Implementation show 3 errors:
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sysclk_IBUF] >
sysclk_IBUF_inst (IBUF.O) is locked to IOB_X0Y102
and sysclk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y18
[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances
Looking through the forum I've found this solution:
but why this was not shown with older Vivado release? There are some way to avoid such constraints and select anothr pin on the Cmod A7 board or is an hardware trouble and then the only workaround is to update the constraints file with the above directive?
Question
BYTEMAN
Dear Sir,
I've installed the latest Vivado 2021.1 suite and try to compile an old blinky design in VHDL, here below the source code:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity blinky is -- Port ( ); port ( sysclk : in std_logic; led : buffer std_logic_vector (1 downto 0) ); end blinky; architecture Behavioral of blinky is constant max_count : natural := 48000000; signal Rst : std_logic; begin Rst <= '0'; -- 0 to max_count counter ctr_led : process(sysclk, Rst) variable count : natural range 0 to max_count; begin if Rst = '1' then count := 0; led(0) <= '1'; elsif rising_edge(sysclk) then if count < max_count/2 then count := count + 1; led(0) <= '1'; elsif count < max_count then led(0) <= '0'; count := count + 1; else led(0) <= '1'; count := 0; end if; end if; end process ctr_led; end Behavioral;on the Digilent Cmod-A7-Master.xdc file I've uncommented following lines (clock and led):
## This file is a general .xdc for the CmodA7 rev. B ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## 12 MHz Clock Signal set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_14 Sch=gclk create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {sysclk}]; ## LEDs set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L12N_T1_MRCC_16 Sch=led[1] set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L13P_T2_MRCC_16 Sch=led[2] ## RGB LED #set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L14N_T2_SRCC_16 Sch=led0_b #set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L13N_T2_MRCC_16 Sch=led0_g #set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L14P_T2_SRCC_16 Sch=led0_rSynthesis give no errors but Implementation show 3 errors:
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sysclk_IBUF] > sysclk_IBUF_inst (IBUF.O) is locked to IOB_X0Y102 and sysclk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y18 [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. [Common 17-69] Command failed: Placer could not place all instancesLooking through the forum I've found this solution:
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
but why this was not shown with older Vivado release? There are some way to avoid such constraints and select anothr pin on the Cmod A7 board or is an hardware trouble and then the only workaround is to update the constraints file with the above directive?
Thanks and best regards.
Edited by BYTEMANLink to comment
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