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FPGA Proto. by SystemVerilog ex. book: Is Mealy machine–based edge detector valid?


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Hi all,

I'm working my way through 'FPGA Prototyping by SystemVerilog examples' book from P. P. Chu.

I'm a bit confused about the Mealy machine based edge detector in section 5.3.1. I'll copy the source code below.

It looks like if a rising edge occurs immediately before the rising edge of the clock, the resulting 'tick' pulse can be super short. So short in fact, that it doesn't even show up in simulation (see first two pulses in attached waveform). Isn't this a recipe for missing rising edges?

This book comes highly recommended as a resource for learning FPGA programming, so it's probably me making a mistake here, not the book, but I don't see it.

Thanks for any insight.

Ruben.

module edge_detect_mealy
   (
    input  logic clk, reset,
    input  logic level,
    output logic tick
   );

   // fsm state type
   typedef enum {zero, one} state_type;

   // signal declaration
   state_type state_reg, state_next;

   // state register
    always_ff @(posedge clk, posedge reset)
       if (reset)
          state_reg <= zero;
       else
          state_reg <= state_next;

   // next-state logic and output logic
   always_comb
   begin
      state_next = state_reg;  // default state: the same
      tick = 1'b0;             // default output: 0
      case (state_reg)
         zero:
            if (level)
               begin
                  tick = 1'b1;
                  state_next = one;
               end
         one:
            if (~level)
               state_next = zero;
         default: state_next = zero;
      endcase
   end
endmodule

mealy_wave.png

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Adding fuel to the fire:

Whether or not the tick pulse appears depends on whether you use non-blocking or blocking assignment in your testbench. If you observe the signals inside the mealy_edge_detect module as well, you can see that the state register is toggling as expected, but that since there is no delay in the simulation between the level rising edge and the state transition (when blocking assignment is used), the tick pulse never fires (or in reality very briefly fires, as you mention).

-Arthur

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Thank you Arthur. I am currently using blocking assignments (see my naive testbench code below). As a beginner I have yet to learn about the the subtleties of non-blocking vs. blocking assignment in the context of a testbench, but if the upshot is that it makes the level rising edge fall at a more convenient time relative to the state transition, wouldn't I be masking an issue instead of finding one with my testbench?

Or am I looking at this wrong and will there in practice always be a noticeable pulse due to propagation delay through the state register?

module dual_edge_detect_sim();
    localparam T=10;
    logic clk, reset;
    logic level;
    logic tick;
   
    edge_detect_mealy uut(.*);
    
    //clk
    always begin
        clk = 1'b1;
        #(T/2);
        clk = 1'b0;
        #(T/2);
    end
     
    //reset
    initial
    begin  
        reset = 1'b1;
        level = 1'b0;
        #(T);
        reset = 1'b0;
        #(2*T);
        level = 1'b1;
        #(5*T);
        level = 1'b0;
        #(5*T);
        level = 1'b1;
        @(posedge clk);
        #(T/4);
        level = 1'b0;
        @(negedge clk);
        #(5*T);
         level = 1'b1;
        #(5*T);
        level = 1'b0;
        #(5*T);
        level = 1'b1;
        @(posedge clk);
        #(T/4);
        level = 1'b0;
        @(negedge clk);
        #(5.5*T);
        $stop;
    end
endmodule

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