I'm working my way through 'FPGA Prototyping by SystemVerilog examples' book from P. P. Chu.
I'm a bit confused about the Mealy machine based edge detector in section 5.3.1. I'll copy the source code below.
It looks like if a rising edge occurs immediately before the rising edge of the clock, the resulting 'tick' pulse can be super short. So short in fact, that it doesn't even show up in simulation (see first two pulses in attached waveform). Isn't this a recipe for missing rising edges?
This book comes highly recommended as a resource for learning FPGA programming, so it's probably me making a mistake here, not the book, but I don't see it.
// fsm state type
typedef enum {zero, one} state_type;
// signal declaration
state_type state_reg, state_next;
// state register
always_ff @(posedge clk, posedge reset)
if (reset)
state_reg <= zero;
else
state_reg <= state_next;
// next-state logic and output logic
always_comb
begin
state_next = state_reg; // default state: the same
tick = 1'b0; // default output: 0
case (state_reg)
zero:
if (level)
begin
tick = 1'b1;
state_next = one;
end
one:
if (~level)
state_next = zero;
default: state_next = zero;
endcase
end
endmodule
Question
epsilon
Hi all,
I'm working my way through 'FPGA Prototyping by SystemVerilog examples' book from P. P. Chu.
I'm a bit confused about the Mealy machine based edge detector in section 5.3.1. I'll copy the source code below.
It looks like if a rising edge occurs immediately before the rising edge of the clock, the resulting 'tick' pulse can be super short. So short in fact, that it doesn't even show up in simulation (see first two pulses in attached waveform). Isn't this a recipe for missing rising edges?
This book comes highly recommended as a resource for learning FPGA programming, so it's probably me making a mistake here, not the book, but I don't see it.
Thanks for any insight.
Ruben.
module edge_detect_mealy
(
input logic clk, reset,
input logic level,
output logic tick
);
// fsm state type
typedef enum {zero, one} state_type;
// signal declaration
state_type state_reg, state_next;
// state register
always_ff @(posedge clk, posedge reset)
if (reset)
state_reg <= zero;
else
state_reg <= state_next;
// next-state logic and output logic
always_comb
begin
state_next = state_reg; // default state: the same
tick = 1'b0; // default output: 0
case (state_reg)
zero:
if (level)
begin
tick = 1'b1;
state_next = one;
end
one:
if (~level)
state_next = zero;
default: state_next = zero;
endcase
end
endmodule
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