• 0

NetFPGA-1G-CML


Question

I've recently stared using this board. There is very limited support from CM Labs; their web site doesn't even mention hardware. I was able to get some, not particularly useful, information through an email contact.

I have the Rev F board. The current schematics are for Rev E.

What is the difference between the current schematics and my board?

The Ethernet PHYs run a 1.8V and timing is a bit hairy, compared to the simpler Digilent board designs. What are the PHY receiver data and control PCB trace lengths?

Since Digilent provides the schematic and user manual documentation you would see to be the only source for support.

Link to post
Share on other sites

6 answers to this question

Recommended Posts

  • 0

Hi @zygot,

The Rev F schematics are available on the 1G CML Resource Center (https://reference.digilentinc.com/programmable-logic/netfpga-1g-cml/start). I asked about the trace lengths and got some details that I have attached. I don't know exactly which signals you were looking for in particular.

In terms of support, what I have been told (at least this was the case last year) is that Digilent will do some hardware error support, but if you are not able to get help from the NetFPGA mailing list (links for it are available here: https://netfpga.org/site/#/systems/2netfpga-1g-cml/support/) then you should be able to get support including software support from CML, via the email support (at) cmlab (dot) biz.

Let me know if you have any questions.

Thanks,
JColvin

NetFPGA-CML RXD trace lengths.txt

Link to post
Share on other sites
  • 0
12 hours ago, JColvin said:

I don't know exactly which signals you were looking for in particular.

Thanks. I need the routing lengths of the Ethernet PHY rgmii_rxd and rgmii_rx_ctl traces, as you've provided.

Link to post
Share on other sites
  • 0

Hi @zygot,

To confirm, since I can't quite tell from the way you phrased it, the provided trace lengths did detail the rx_ctl and rxd traces you needed, correct? As far as I can tell from the RTL8211E datasheet, the RXCTL pin is on the same pin location as RXDV (for a different pin package) which both have the pin name of PHY_AD2, and the trace length document seems to list the RXDV_X trace lengths.

Thanks,
JColvin

Link to post
Share on other sites
  • 0
Posted (edited)

Yes, I think that you got me the information that I need. The reported lengths seem to be reasonable, from looking at the board.

For most of Digilent's FPGA boards with a 1GbE PHY you don't need trickery to convert the PHY rgmii signals into gmii signals. For this particular board, I found that I had to implement IDELAY. No doubt one reason for that is that the PHY come out of reset with the 2 ns RxD delay enabled. The NetFPGA-1G-CML PHY interfaces are 1.8V, unlike the usual Digilent boards. I'm not sure if that's an issue or not. Since I'm going to do have the IDELAY expense in my designs I might as well do it correctly.

I know that this is another topic but I've run into a curious issue with Vivado 2020.2 and the Xilinx PCIe 3.3 core. I was trying to port the Xilybus PCIe demo for the KC705 to the NetFPGA board. No bug issues except that Vivado just won't allow me to assign the GTX lanes to the proper bank or pins. Evidently, from what I can see from the reference projects earlier tools like ISE work. I know this because I've connected the board to a PC running Ubuntu an the board shows up as a PCIe device ( this is using the default application in BPI ). Anyone you know around Digilent familiar with Xilinx PCIe implementations who might have some idea how to beat Vivado into submission?

With ISE, it seems that you can assign particular GTX transceivers with the ucf constraints. Vivado doesn't seem to be interested in the user's opinion about those assignments.

Oh, one more question. Does anyone know of a Xilinx document where you can find the transceiver or PCIe block locations for a particular device and package that agrees with the tool constraints nomenclature?

thanks,

Edited by zygot
Link to post
Share on other sites
  • 0

Hi @zygot,

I'll have to ask about the best way to force Vivado to obey, but regarding the transceiver/PCIe block locations, is figure A-5 page 350 on UG476, https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf#G10.276349, what you are looking for (presuming you are asking about the Kintex 325 on the CML board)? Or did I misunderstand the question?

Thanks,
JColvin

Link to post
Share on other sites
  • 0

Thanks @JColvin,

BTW. After realizing that the ISE 14.7 installed on my Win10 box was willing to use my K325T license I was able to port the Xillybus PCIe demo for the KC705 to the NetFPGA-1G-CML target. At least I know that the hardware is functioning as I've been able to read/write to the FPGA using PCIe.

Still, I'd like to have the option of using Vivado.

Now that I know that I can use the Xilinx PCIe block with a modern Linux Kernel the NetFPGA-1G-CML might just become my favorite platform.

Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now