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FIFO Block Design Using Verilog


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So I am designing a FIFO for the Digilent USB104 A7 FPGA. I have two goals for it. First a "Hello World" type of test to demonstrate the FIFO bus outputting data to the FTDI device.  Second a loopback using the FIFO where the input gets routed back to the output so whatever we send into the FTDI device comes right back out. Here is my code for the FIFO:

module FIFOAXI( prog_clko, prog_rxen, RD, WR, EN, prog_txen, RST, EMPTY, FULL ); 

input prog_clko, RD, WR, EN, RST;
output  EMPTY, FULL;

input  prog_rxen;
output reg [7:0] prog_txen; 
reg [2:0]  Count = 0; 
reg [31:0] FIFO [0:7]; 
reg [2:0]  readCounter = 0, 
writeCounter = 0; 

assign EMPTY = (Count==0)? 1'b1:1'b0; 
assign FULL = (Count==8)? 1'b1:1'b0; 
always @ (posedge  prog_clko) 
begin 
 if (EN==0); 
 else begin 
  if (RST) begin 
   readCounter = 0; 
   writeCounter = 0; 
  end 
  
  else if (RD ==1'b1 && Count!=0) begin 
   prog_txen  = FIFO[readCounter]; 
   readCounter = readCounter+1; 
  end 

  else if (WR==1'b1 && Count<8) begin
   FIFO[writeCounter]  = prog_rxen; 
   writeCounter  = writeCounter+1; 
  end 
  
  else; 
 end 

 if (writeCounter==8) 
  writeCounter=0;
  
 else if (readCounter==8) 
  readCounter=0; 
 else;

 if (readCounter > writeCounter) begin 
  Count=readCounter-writeCounter; 
 end 

 else if (writeCounter > readCounter) 
  Count=writeCounter-readCounter; 
 else;

end 
endmodule

 

I also have attached my block design. I want to use the verilog code and implement it into the block design. I have done this using the add module. My question is, do I need to add anything else for it to work or is my block design correct already?

verilog block.png

Edited by rmccormack1
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Hi @rmccormack1

Your verilog code has some issues. For example, writeCounter, readCounter, and Count should never hold the value of 8 - required to have some of the if statements and ternaries do anything - since they are all three bits wide, meaning that FULL is never asserted.

The block design also presents issues, depending on your constraints. What pin locations are all of your ports connected to in your XDC? The prog_txen port should only be a single bit wide, and you are entirely missing the prog_d data bus. The USB104 A7's reference manual has some more information on which ports should be used when working with the DPTI interface. https://reference.digilentinc.com/programmable-logic/usb104a7/reference-manual#dpti_parallel_data_transfer_interface

It might be worthwhile to make sure that you can send data through the DPTI in one direction before attempting the loopback - something like writing an incrementing stream of bytes into the USB controller's emulated FIFO from the FPGA and using the Adept API to read them on the PC side. As an analogy, it would be more difficult to design a UART transmitter/receiver and a loopback than it would be to just make a transmitter, make sure it works, then design the receiver, make sure it works, then combine the two.

Thanks,

Arthur

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