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cmod a7 xadc, which sequencer channels can I use from the 2 analog inputs?


charkster

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I have read UG480. It looks like only specific sequencer channels can be used with the 2 pins which are available on the cmod a7. Does anyone know which channels can be used? I have tried Vp/Vn but this does not appear to give me the results I expected. I am putting 0.2V on the analog input and am expecting a 12bit value of 820 decimal.

Also, I was expecting the XADC Wizard to allow a static configuration where the channel_out[4:0] could be tied to the daddr_in[6:0] and the do_out[15:0] would always show valid channel conversion values when the busy_out is low. I have seen examples of the eoc_out signal being tied to the den_in input which looks like a good way to keep the sequencer always running.

https://sites.google.com/a/umn.edu/mxp-fpga/home/vivado-notes/xadc/single-channel-continuous-mode-example

I was not able to get this working, but it appears to be the simplest/best way to configure the XADC. Does anyone have this method working? 

Thanks. 

 

 

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Hi @charkster,

Only AIN15_P (package pin G3) and AIN16_P (package pin H2) are connected to AIN15 and AIN16, respectively. The negative input of these pairs (AIN15_N / G2 and AIN16_N / J2) are tied to ground, which you can see one page 1 of the Cmod A7 schematic: https://reference.digilentinc.com/_media/reference/programmable-logic/cmod-a7/cmod_a7_sch_rev_c0.pdf. As you noted in the .xdc, AIN15 is connected specifically to vaux4 and AIN16 is specifically connected to vaux12; you can see confirmation of this on page 3 of the schematic on bank 35 where those two inputs are connected to AD4P and AD12P.

I also wanted to clarify that if you provide a 0.2 V signal to one of the inputs, you will instead get a decimal value around 250 (248 in ideal conditions which I have never encountered). The reason for this is because the Cmod A7 implements a resistor divider to allow the FPGA to safely handle between 0 V and 3.3 V rather than the typical restriction of 0 V to 1 V.

As for why the negatively tied inputs are listed in the .xdc, I suspect it's so Vivado can route the _n inputs to the XADC wizard. There is an XADC demo for the Cmod A7 available on it's Resource Center in case you haven't seen it.

Let me know if you have any questions about this.

Thanks,
JColvin

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After looking at ug475_7Series_Pkg_Pinout.pdf page 98 (CPG236) pins G2, G3, J2 and H2 are able to connect to any AD0P/AD0N−AD15P/AD15N signal. In looking at the default pin constraint file for the cmod a7, there is a comment for using pins 15 and 16:

## Analog XADC Pins
## Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12
#set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15]
#set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15]
#set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16]
#set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16]

I will try to specifically use vaux4. Are the G2 and G3 pins both tied to pin 15? Are G2 and J2 tied to analog ground? If they are, why would they appear in the pin constraint file?

 

Thanks.

Edited by charkster
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Hi @JColvin,

Thank you very much!! I should have looked at the schematic. I raised pin 15 voltage to 3.3V and saw full range on the 12bit value. I have a really good XADC configuration which is working well for me. I will post it tomorrow if others are interested. It converts a single channel continuously and has a data valid signal.... very simple.

Great support is why my company buys Digilent.

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I decided to configure one XADC resource to be DRP interface, single channel, event triggered with adc_clk being 4 dclk cycles. No averaging, adc offset and gain correction, sensor offset and gain correction (sensor is probably not needed). Vaux4 selected.

I am able to enable/disable the adc with a config register. I start the first conversion with a rise edge detect of the config register and then the eoc_out triggers until the config register is written low. 

Constraints 

## Analog XADC Pins
## Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12
set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { vauxn4 }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15]
set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { vauxp4 }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15]
#set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16]
#set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16]

RTL file:

assign adc_trigger = (cfg_enable && eoc_out) || pos_edge_enable;
  
   xadc_wiz_0 u_xadc_wiz_0 // DRP single channel event triggered 4 clocks, no averaging, adc offset and gain correction, sensor offset and gain correction, no alarms,
   ( .convst_in   (adc_trigger),     // input
     .daddr_in    (7'h14),           // input [6:0] address x14 is Vauxp4/Vauxn4 result
     .dclk_in     (clk_250mhz),      // input
     .reset_in    (~rst_n_250mhz),   // input
     .di_in       (16'd0),           // input [15:0]
     .dwe_in      (1'b0),            // input
     .den_in      (1'b0),            // input
     .do_out      (adc_data),        // output [15:0]
     .drdy_out    (adc_ready),       // output
     .busy_out    (busy),            // output
     .channel_out (),                // output [4:0]
     .eoc_out,                       // output
     .eos_out     (),                // output
     .alarm_out   (),                // output    
     .vauxp4,                        // input analog
     .vauxn4,                        // input gnd
     .vp_in       (),                // input, board schematic has this at anaground
     .vn_in       ()                 // input, board schematic has this at anaground
    );

 

Edited by charkster
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