PMODi2s2 Arty z7-10

[Sheraz]

Hi Everyone!

I need help using the following pmodi2s2 module: -
https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/

I want to use it to sample audio data from microphone only. So, I've added the i2s receiver IP into my block diagram (attached) and run block automation.

Following is the documentation of the IP core I used: -
https://www.xilinx.com/support/documentation/ip_documentation/i2s/v1_0/pg308-i2s.pdf

The following is a reference manual for the above mentioned PMOD module: -

https://reference.digilentinc.com/pmod/pmodi2s2/reference-manual

I also created an extra clock in PL fabric named FCLK_CLK1 (11.289MHz requested and got 11.290323 MHz).

I couldn't find a PMOD core for the said module so I guessed I'll "make-external" and "constraint" the pins on to the PMOD header in a .xdc file.

Now, I don't know what to connect where except for the lrclk_out, sclk_out and sdata_0_in which are obvious from their names. Rest of the configuration is auto generated by block automation.

I'm particularly confused regarding the clocking and reset configuration.

Please help me out on this I'll highly appreciate.

[artvvb]

Hi Sheraz,

I'm not sure if anyone around here is familiar with that particular I2S IP, as it looks like it was released quite recently. As you might have seen in other threads and on the I2S2's resource center, there are a couple of different I2S demos/examples we've put together over the years - I recommend starting with these instead.

That said, I'll try to provide some general comments on potential issues in getting this IP connected up:

The AXI-stream master interface needs to be connected to something downstream to consume the data - this will be how the audio data exits the receiver. An AXI DMA is a common way of pushing this data into DDR so that the Zynq PS can do stuff with it. Since the I2S IP's stream interface doesn't have a tlast signal, you will need to provide that yourself - probably requiring something along the lines of detecting the start/end of a block based on the values in tdata (but I'm not sure).

The aud_mclk input should be connected to FCLK_CLK1 and to an external port.

The _axis_ clock should likely be connected to FCLK_CLK0 (and the _axi_ctrl_ clock), with the reset getting tied to the AXI control reset.

irq needs to be connected to the Zynq's IRQ_F2P interrupt port, which needs to be enabled in the Zynq configuration.

Thanks,

Arthur
 

[Sheraz]

Edit 1: I'm using Vivado 2018.2 on Windows 10 Home OS build 19042.1052

I made a custom IP from the files provided in example project available at https://github.com/Digilent/Pmod-I2S2

The IP works at 22.591 MHz procuring a 44.1kHz stereo input of 24-bit depth as AXI-4 stream through its master port.

The same kind of signal can be used for the Transmission as well through its slave port.

So I put a loop back so I'd be sure the signal is received correctly.

I have used a clock converter to match it to the clock I use for the rest of the PL.

It doesn't have internal buffering so cascaded a AXI-4 stream FIFO with it.
Following is my test design: -

Attached is the waveform that I capture using system ILA.

The signal TLAST is asserted every second word hence marking a packet of 2 (3-byte) words.

In my bare-metal code in SDK I use the interrupt mode but the transfer length confuses me.

Please suggest what should be my MAX_PKT_LEN parameter in following command: -

Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) RxBufferPtr, MAX_PKT_LEN , XAXIDMA_DEVICE_TO_DMA);

waveform: -

block diagram: -

Moreover I seem to have an issue with my custom IP core.

Following two warnings appear in the IP editor and it does not appear as a valid interface when connecting board components. So I need to specify pin ports in constraints as well as the diagram.

[IP_Flow 19-570] Bus Interface 'pmod_i2s2': Cannot find bus definition file for "digilentinc.com:interface:pmod:1.0"
[IP_Flow 19-569] Bus Interface 'pmod_i2s2': Cannot find bus abstraction file for "digilentinc.com:interface:pmod_rtl:1.0"

Edited July 10, 2021 by Sheraz
added tools version and Host system information

[artvvb]

Hi Sheraz,

I think that MAX_PKT_LEN is primarily there to inform the drivers about the size of the chunk of memory that it is allowed to put data into - it should match the size of the array that RxBufferPtr is pointing at, which also needs to be equal to or larger than the size of the longest packet that might be received, 2 words in this case.

The missing bus interface is likely due to not including the [vivado-library](https://github.com/Digilent/vivado-library) repository as an IP repository in the project - it contains the definition of the Pmod interface used in the board files. That said, getting the Pmod interface working with a custom IP takes extra work that is not necessary here. I'd recommend either using the Pmod Bridge IP contained in vivado-library to connect to GPIO interfaces on your custom IP and to the board file interface, or to remove the Pmod interface entirely and just manually constrain the individual pins (which would then not be associated with any interface).

Thanks,

Arthur