How can i reach 800 Mb/s on Nexys Video DDR3 ?

[ManuelPA]

I have implemented the DDR3 on the Nexys VIDEO as shown in this tutorial

https://reference.digilentinc.com/nexys-video/gsmb

so my question is how can i mofidfied the IP MIG for reach 800 Mb/s on the nexys video?

when i open the IP for modified teh parameters in clock period i set 2500 ps, input clock period 1250 ps (800 MHz), system clock : No buffer, Reference clock: Diferencial, clk_reference with pin number R4/T4, so when i run the synthesis occurs a problem in the clk_ref

Note: some of the setting of my  IP MIG

In this part i connect the pins R4 and T4 in the CLK_ref_p and CLK_REF_n. but in the synthesis occurs a problem

[D@n]

While I haven't used this memory generator before, it occurrs to me that the singular characteristic of DDR memory is that it clocks data on both rising and falling edge of the clock.  I can't be certain, but I can imagine that 400MHz clock is exactly what you are looking for.

Dan

[ManuelPA]

14 hours ago, D@n said:

While I haven't used this memory generator before, it occurrs to me that the singular characteristic of DDR memory is that it clocks data on both rising and falling edge of the clock.  I can't be certain, but I can imagine that 400MHz clock is exactly what you are looking for.

Dan

But in the tutorial of digilent the "pin : sys_clk_i" has a clock of 200 MHz, so the DDR3 is working on that frequency or the IP MIG made it works at 400 MHz without customizing?

[D@n]

Good question.  Two thoughts:

1) Isn't the MIG interface determined by the board configuration file?  Were you able to incorporate the Nexys Video board configuration file into Vivado?

2) Based upon your last comment, even if you didn't have the board configuration file, shouldn't the "Input Clock Period" in the second image be the 200MHz frequency of "sys_clk_i" and not the 800MHz frequency you've placed in it?

Dan

[ManuelPA]

Thanks Dan but i still in the same problem whit the clk_ref_p/n, when i run the synthesis it ocurrs a problem

[D@n]

Can you copy the error you are getting into your question?  It would help to know what's going on.

Thanks,

Dan

[ManuelPA]

When i made the IP MIG configuration and run the RTL analysis on the schematic, appears this:  (when i dont set anything of the IP configuration the pins "clk_ref_p/n" dont appear and the following message does not appear ).

and i cant asing the ports specialy the T4

[D@n]

Let me answer a question not specifically addressed above, but underlying what you are asking about: what speed will the memory run at, when configured via the board project file?

Since I'm using Vivado 2014.4, I downloaded the project file from here.  Within that zip file is a nexys_video directory, and then further down there's a mig.prj file within that.  This .prj file specifies the values for the memory interface generator as would be appropriate for the Nexys Video board.  Within that file, the TimePeriod for the memory interface is specified at 2500 ps.  This corresponds to a memory clock of 400MHz.  Further, given that DDR3 memory transfers on both edges of the clock, that actually corresponds to a memory transfer rate of 800Mb/s on each data wire.  Looking down further through the memory configuration, you'll see that there are 16 data pins to this memory, so it should theoretically support a 1.6GB/s data rate.

That's the data transfer rate only.

Also at issue is the row access and column access latencies.  The CAS Latency for reading is listed as '6' within the file, and '5' for writing.  I'm not sure if these are nanoseconds, clocks, or ... what.  But the bottom line is that you can't suddenly start reading or writing from the chip.  From the beginning of your AXI bus access to read or write the memory on the chip to the time it is actually read or written, there will be a setup delay.  After that setup delay the chip will transfer data at your 1.6GB/s rate ... as long as your bus interaction will support streaming.

The MIG project file also specifies that the memory can handle a burst length of 8, which I would gather references 8 transfers of 16 bits, or equivalently 16-byte bursts.  It's not clear whether or not the memory controller will sustain burst upon burst transfers with no latency between bursts.

Also, you should keep in mind that, as with any DRAM controller, the memory will need to be taken off line for refresh cycles.  Hence your memory access times will vary depending where you are in the refresh cycle logic.  Somtimes you might find it takes N clocks to access a particular memory address, sometimes it will take longer.

I guess my point is, yes it will transfer at 1.6GB/s, but before you plan on that figure be aware that your actual mileage might vary.  You might need to run some tests within your application to see what data rates are actually achievable.

Finally, the wikipedia article on DDR3 SDRAMs is pretty decent--that and the basic SDRAM article.  Feel free to take a peek at those for more information.

Dan