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Zedboard - Vivado 2020.2


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Hey all,

I've got a small and probably stupid problem. Upgraded my Vivado to version 2020.2 and setup the basic Zynq hello world tutorial but it seems nothing comes out of the UART side. Little summary with print screens to make it as clear as possible...

So first of all, I've downloaded the latest board files from Digilent (Github) and installed them accordantly. Next created a rudimentary board design with the Zynq processing system instantiated and UART 1 strapped to MIO 48 - 49 as is required (see print screen below). Board design check completes without any problem. 

image.thumb.png.5284f326c7b7b5e6011a737f6680298b.png

 

Within the platform project, double checked that ps7_uart_1 is used for stdin/stdout

image.png.99b529321a9d32096f7f1e3c7c26f287.png

 

Then the default hello world application is used and programmed correctly to the FPGA (blue led is on after programming the FPGA) but is seems the "hello world" via the UART is not coming trough (put the "print("Hello World\n\r");" in a while(true) loop to make sure I didn't miss it). Drivers are correctly installed and the COM port (5) is recognized correctly as well as the USB Serial Convertor / USB to UART Adapter.

image.png.e1519d4d7dcab15585b33d75076da08c.png

 

Jumpers JP7-JP11 are in the JTAG position so configuration wise this should be oké.

Interesting thing, if I load in via the SD card the default image that is provided with the Zedboard, UART is working just fine so I'm wondering where the problem is hidden here? 
 

Looking forward to some input :).

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Posted (edited)

Hey @JColvin,

Thanks for the response. Considering the board file, indeed I've taken the one from Digilent (assumed this was the maintained one since Avnet didn't provide support anymore but Digilent does (read this on a certain forum post). Nevertheless, first followed your advise and installed the board file directly from Avnets Github page (bdf/zedboard/1.4 at master · Avnet/bdf · GitHub), which should, accordantly to the commit messages, support Vivado 2020.2. But this is for revision D I've noticed.

Nevertheless, this didn't resolve the problem. Just double checked the revision, and the board is revision E.

Considering the SD card project, there was an SD card delivered with the Zedboard which contained a Linux image. If you go on the Digilent website and search for the images that are present then you'll see the SD card being delivered with the board (https://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc-development-board/).

Just double checked if nothing was wrong with the Zedboard so I've thrown on an custom IP for the UFMT600X board that is connected via the FMC header and using that as a data streamer (via USB30.) towards the PC (without any Zynq instantiation, so the data generator + FIFO USB3.0 bridge where implemented as custom logic) and that worked just fine so I guess there is nothing wrong with the FPGA itself. 

I came across another post where the person had the same problem with revision E boards (https://forum.digilentinc.com/topic/20531-zedboard-rev-e/), so is there a possibility to get an revision E board file and test it?

 

// Edit --> SOLUTION

Just founded this document from a previous thread here on the forum and since the memory parts on the Zedboard are of 4Gb  (https://zedboardupgrade.s3.us-east-2.amazonaws.com/ZedBoard+Rev+E+project+update+procedure.pdf?_ga=2.197137327.1072668274.1623081646-1457440089.1620987456). This resolved the problem, thus is there a board file for revision E available or are the memory components not instantiated via the board design and this wouldn't resolve anything? A permanent fix would be nice for this :-)?

 

Edited by tommienator
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Hi @tommienator,

It sounds like you've checked everything I would normally recommend to look at. It shouldn't make a difference in terms of the UART, but I'm presuming that when you selected the Zedboard board file during the initial project creation phase, you selected the one created by Digilent as opposed to Avnet. I just created a 2020.2 Vivado/Vitis project for the Zedboard and tested both the built in Hello World project and the test project that is created as part of Digilent's Getting Started with Vivado's IP Integrator Guide, but did not run into any issues.

I guess some questions that I have since the SD card project is working (I'm not certain which particular project that is, the Zedboard I have doesn't have a designated SD card with it) would be what revision of the Zedboard do you have and what baud rate is your serial terminal set to? Based on your screenshots, your BSP settings and MIO configuration for UART1 should be correct.

Thanks,
JColvin

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Hi @tommienator,

I can see how my initial wording didn't make sense, I did mean to imply that I used the Digilent board file for the Zedboard, as that is the one Digilent has control over (i.e. maintenance/knowledge of if it gets updated), rather than the Avnet board file.

To my knowledge, all of the Rev E boards have either been reworked so that they use the Rev D memory part or you can go through the update procedure so that the various getting started materials that were created by Avnet and hosted on their website work with the larger memory part that was initially loaded. Rev F of the Zedboard should have memory parts that are compatible by default with any existing getting started materials. There has not been any changes that have been made to the board files themselves on either Digilent's or Avnet's side for any version of the Zedboard that I can recall.

I didn't realize the SD card that came with the Zedboard had a Linux image already existing on it, though I now see the OOB zip file on the Zedboard's Resource Center that I somehow missed yesterday. I confirmed the OOB UART works on my Rev D as well, though I do not have a Rev E board of any kind (4 Gb memory or otherwise) to readily test.

Let me know how the update procedure goes for you.

Thanks,
JColvin

 

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Hey @JColvin,

In the end I've could fix the problem with the tutorial given by Digilent (https://zedboardupgrade.s3.us-east-2.amazonaws.com/ZedBoard+Rev+E+project+update+procedure.pdf?_ga=2.236277057.1100890869.1622904314-1810490008.1617456326). On the other hand I don't see any things considering REV E of the Zedboard on the website of Avnet (https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard/). 

 

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Hi @tommienator,

I'm glad to hear the update procedure worked.

I'm not surprised to see that Avnet doesn't have any new material for the Zedboard, including Rev F which (to my knowledge) has been in production for 6+ months and addressed various parts (looks like inductors based on what is listed on the first page of the schematic) that went EoL. I don't know if and when their site will get updated.

Thanks,
JColvin

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