vivado project with using DDR3

[Golan Asher Audiopixels]

Hello,

Do you have in your web, Vivado project contain MIG, DDR interface, that works well on the board of Digilent: ARTY-S7 (with Spartan7, S50|) ?

If yes, can you send link, that i can download it ?

Regards,

Golan Asher.

[JColvin]

Hi @Golan Asher Audiopixels,

I don't believe we have a pre-existing demo for the Arty S7-50 that integrates the MIG and DDR.

What I would recommend is that you go through our Getting Started with Vivado IP Integrator guide which walks you through creating a block design integrating the MIG and DDR into a Microblaze based design.

Let me know if you have any questions.

Thanks,
JColvin

[Golan Asher Audiopixels]

Hi,

I read in your document: ArtyS7 FPGA Board Reference Manual, at chapter: DDR3 Memory:

For clocking, it is recommending that the System clock be set to “Single-ended” and connected directly to the
onboard 100MHz oscillator on pin R2. The Reference clock should be set to “no buffer” and can be connected to a
200 MHz clock generated from a clocking wizard elsewhere in the design

So in that case, as I understand, the signal DDR3_CLK100, that connected to PIN of FPGA: R2, connected directly in the FPGA to sys_clk of MIG (and not using DCM with distributing clocks).

What clock should I use to other logic in my design ?

I understand also that you took off from mounting the additional oscillator in the card, signal name: UCLK, that connected to F14 of the FPGA. It is also written in Schematic: "No Load".

Do I need to mount that Oscillator ? (IC2) or do you have other solution ?

arty-s7_rm.cleaned.pdf