Cmod A7 Out of Box Demo Not Working Correctly

[palmervb]

Hello All,

I am very new to learning how to program FPGAs and right now I am working with the CMod A-7 35T board. Apologies if this is a super simple question, but I have been having some issues with using the CMod A-7 Out of Box Demo found on this page (https://reference.digilentinc.com/programmable-logic/cmod-a7/start). I have been able to successfully program my FPGA with both the GPIO demo, the XADC demo, and I have gone through the "Getting Started with Vivado" tutorial as well, so I have been able to program my FPGA both to the SRAM and Quad SPI flash. However I am not getting the expected result programming the Out of Box Demo, and I'm not sure if I am doing something wrong or if there is a known issue with this demo.

I initially used tutorial found here (https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start and https://github.com/Digilent/Cmod-A7-35T-OOB?_ga=2.230333396.953160938.1622227269-1673101782.1621522474) which uses Vivado 2018.2 and Vivado SDK. I am currently running Vivado 2020.2 with Vitis, so I could not follow this tutorial all of the way through. I dug around and found this page (https://reference.digilentinc.com/programmable-logic/cmod-a7/demos/oob) which lists the tutorial as using 2020.1, but the page is listed as under construction. Whether I followed the 2020.1 tutorial, or just opened the program from the 2018.2 files and programmed the FPGA through the hardware manager on Vivado, the result is the same; the LED by pin 24 stays bright red, and one of the LEDs near the tricolor LED stays bright orange. Neither of the buttons cause any change on the board itself, and nothing shows up in Tera Term.

I do not get any error messages when I generate a bitstream or program the FPGA, but I do get an alert on Vivado that "The design contains IP with major version changes. Please refer to the Change Log to understand the impact of upgrading an IP with major version change in your design, prior to upgrading." which I assume is at least part of the issue, but I don't know exactly where that is or how I would make those changes.

Thank you all in advance and hopefully I gave you enough information to answer my question. If there's anything else I would need tp provide let me know.

[artvvb]

Hi @palmervb

I tested the 2020.1 page's steps in Vitis 2020.2 today, and it is now functional. There was a step missing which was preventing the Vitis project from building due to some incorrect paths which must be manually updated. These steps have now been added to the document. Please make sure you are using the release files linked from the 2020.1 page.

When opening the Vivado project (as the optional steps discuss), you are likely to also need to use the Tools > Report IP Status option, upgrade all IP, and (maybe) make changes required by new versions of the IP in the project. This is what the warning about major version changes in an IP is indicating. If an IP version goes from (for example) 4.1 to 4.2, the minor version has incremented, and typically won't require changes to the design. If the IP version goes from 2.1 to 3.1, then the major version has incremented and changes are likely required - potentially some port on the IP's name has changed, or a configuration parameter has a different name, or there may be some major functional change that requires additional changes to the surrounding hardware design. In any of these cases, it likely requires going to the datasheets of the IP involved in order to get it working in the new version.

Thanks,

Arthur

[palmervb]

Awesome thank you for your help! Project works now.