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Zynq - memory caching issue for external ADC results


james_h_66

Question

Greetings!  I'm almost done in getting my external ADC talking to my Arty Z7 board.  In one of my last steps, I am getting some incorrect results, which I *think* is a caching issue.

My setup:

AD7606B EVAL board connected to Arty Z7-7020 using parallel hardware interface

On the AD7606B, there are 8 analog inputs:

Inputs 1, 5, and 8 are tied to my test voltage power supply

Inputs 2, 3, 4, 6, and 7 are shorted together (that is, tied to ground).

In the code, I think I have flushed the cache region that my ADC logic block writes to.  When I run the code using the debugger (in the screenshot), I have two separate windows:

the serial port terminal (bottom left in screenshot), where I use "printf" statements to print out the 8 ADC channels (ADC channels "1" through "8" --> "array[0]" through "array[7]").  This is giving me WRONG results for ADC channels 5 and 8.

The memory viewer (bottom right in screenshot), where it updates the 8 memory locations every time I pause the debugger.  This window is giving me CORRECT results.

I'm not entirely sure why one is right and the other is not - shouldn't the code and memory map be showing me the same results?

 

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