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Fastest way for reading and writing data


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I am currently using Basys3 board.( Using microblaze soft processor in my design )

I am looking for a way to read and write data into bram quickly. I am using a custom ip to do the computations related to the data. The outputs computed by the ip are then stored into the bram which is then again sent to the ip which processes the data in a different manner this time around and so on.This continues for a few cycles.So data transfer in an out of bram is quite an important factor affecting the peformance of my design.

I went through the method of using Axi dma, i.e., 1. Connecting axi stream interfaces with the custom ip(M_AXIS_MM2S and S_AXIS_S2MM) and 2. (normal)axi interfaces with the bram(through bram controller and then block memory generator) ( using  M_AXI_S2MM and M_AXI_MM2S of the dma).

Part 1: If I am understanding this correctly, then although the data in and out of the custom ip is using axi stream but the data transfer in the Bram is using axi interface only which slows down the design ( here i am assuming that data transfer through axi stream is much faster than (normal) axi which will take a lot of cycles to transfer the data in and out of bram - hence slower design.

So, I would like it if someone could approve or reject ( and then clarify the right answer ) this notion of mine. And if possible tell me a better approach than this for my design.

Part 2 : Although I am currently using Basys 3 Board, in future I will move on to a higher end board and will be eventually using ddr memory for my design instead of bram. So is there a way I can use bram ( in my current board ) which will resemble using ddr : Sort of like a design where my bram acts as a ddr so I can check my ideas for the application as if I was actually using ddr in the higher end board right now and not have to change much when I use this design (of basys 3 board) on the higher end board.

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2 hours ago, hm563562 said:

The outputs computed by the ip are then stored into the bram which is then again sent to the ip which processes the data in a different manner this time around and so on.This continues for a few cycles.So data transfer in an out of bram is quite an important factor affecting the peformance of my design.

Block memory resource in FPGAs are very high data throughout and the fastest ways to transfer data, excluding transceivers. So your soft processor is the bottleneck here. If you are comfortable doing HDL design getting rid of the MicroBlaze would be a good first step. This is especially true for iterative algorithmic computations. I don't know the details of your project of course so this is just my first impulse from reading your post. I don't use soft-processors. 

An alternate design scheme would be to disconnect the data processing from the MicroBlaze and use a state machine to run the algorithm. You might find that the processor is not essential. If you do need the processor for some reason, it would just setup the algorithm, let it run to completion, and then access the results and do with that data as required. Understanding AXI requirements and timing is non-trivial. The MicroBlaze compatible AXI IP may or may not hide the complexity for implementation but it certainly doesn't help with calculating timing parameters for your algorithm.

2 hours ago, hm563562 said:

So is there a way I can use bram ( in my current board ) which will resemble using ddr

Well that depends on how naive you want to be with respect to the inner workings of your design. BRAM is fairly straight-forward, in terms of timing and conceptualization of the details. DDR is not. DDR implementation is also not straight-forward with respect to platform migration of a completed project design. That being said, FPGA vendors are good a hiding the details as long as you are happy with what they give you. Figuring out what it is that they give you might be a hard problem for some project goals. At first reading your project seem to be one of them. The MiG tool allows you to create HDL designs that use the DDR on a particular board but you have to create the logic that controls the read/write operations to the DDR controller. None of the FPGA vendors that I now of, and few FPGA development board vendors are too interested in helping you out with that, because, well it's just better for them if you submit to the Soft Processor vendor IP limited functionality playground.

Any really useful advice requires a bit more information about a few details of your algorithm and what the application needs to do to showcase it. Do you want a PC interface for user control or data transfer or just run the algorithm, detect if the results are correct and measure the throughput? Are you pretty confident of your HDL skills or are you hoping to use the FPGA vendor IP to hide all of the nasty, hard to do implementation details? Those kinds of details separate good useful advice from bad advice. Good advice for me isn't necessarily good advice for you.

Edited by zygot
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