Atlys HDMI J1:IN configuration issue

[chcollin]

Hi,

I've written a simple vhdl core to act as an EDID emulator.
It's basically a PLB Master core, catching interrupts from a PLB Slave XPS_IIC core attached to HDMI SDA/SCL line to manage I2C/DDC protocole.
This core works fine when xps_iic is connected to J3:IN I2C ports (M16 for SCL, M18 for SDA).

However, nothing happens when the xps_iic is connected to J1:IN I2C ports (C13 for SCL, A13 for SDA).
I guess I'm missing something with JP2 and JP4 jumpers.

Can you please tell me the correct jumper settings to have J1:IN hdmi port act the same way as J3:IN ?
Please note that I need for my project to have both J1:IN and J3:IN work together as I'm working with 2 video streams.

Thank you for your help.
 

[chcollin]

Solution posted here

[chcollin]

Also, generating bitstream raises an error with projects using HDMI J1 and J3 as inputs and J2 as output :

Incompatible IOB's are locked to the same bank 0
   Conflicting IO Standards are:
   IO Standard 1: Name = TMDS_33, VREF = NR, VCCO = 3.30, TERM = NONE, DIR =
   OUTPUT, DRIVE_STR = NR
   List of locked IOB's:
   	hdmi_out_0_TMDS_pin<0>
   	hdmi_out_0_TMDS_pin<1>
   	hdmi_out_0_TMDS_pin<2>
   	hdmi_out_0_TMDS_pin<3>
   	hdmi_out_0_TMDSB_pin<0>
   	hdmi_out_0_TMDSB_pin<1>
   	hdmi_out_0_TMDSB_pin<2>
   	hdmi_out_0_TMDSB_pin<3>

   IO Standard 2: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
   BIDIR, DRIVE_STR = 12
   List of locked IOB's:
   	xps_iic_1_Sda
   	xps_iic_1_Scl

   These IO Standards are incompatible due to VCCO mismatch.

Current system.ucf is configured like this (mainly taken from Digilent Atlys HDMI Demo) :

 

#HDMI Out Ports
NET "hdmi_out_0_TMDS_pin(0)"  	  LOC = "D8"  | IOSTANDARD = TMDS_33 ; # Blue
NET "hdmi_out_0_TMDSB_pin(0)"     LOC = "C8"  | IOSTANDARD = TMDS_33 ;
NET "hdmi_out_0_TMDS_pin(2)"  	  LOC = "B8"  | IOSTANDARD = TMDS_33 ; # Red
NET "hdmi_out_0_TMDSB_pin(2)"     LOC = "A8"  | IOSTANDARD = TMDS_33 ;
NET "hdmi_out_0_TMDS_pin(1)"  	  LOC = "C7"  | IOSTANDARD = TMDS_33 ; # Green
NET "hdmi_out_0_TMDSB_pin(1)"     LOC = "A7"  | IOSTANDARD = TMDS_33 ;
NET "hdmi_out_0_TMDS_pin(3)"  	  LOC = "B6"  | IOSTANDARD = TMDS_33 ; # Clock
NET "hdmi_out_0_TMDSB_pin(3)"     LOC = "A6"  | IOSTANDARD = TMDS_33 ;

#HDMI in Ports
NET "hdmi_in_0_TMDS_pin(3)"  	LOC = "H17" |IOSTANDARD = TMDS_33 ; # CLK
NET "hdmi_in_0_TMDSB_pin(3)"  LOC = "H18" |IOSTANDARD = TMDS_33 ;
NET "hdmi_in_0_TMDS_pin(2)"  	LOC = "J16" |IOSTANDARD = TMDS_33 ; # Red
NET "hdmi_in_0_TMDSB_pin(2)"  LOC = "J18" |IOSTANDARD = TMDS_33 ;
NET "hdmi_in_0_TMDS_pin(1)"  	LOC = "L17" |IOSTANDARD = TMDS_33 ; # Green	
NET "hdmi_in_0_TMDSB_pin(1)"  LOC = "L18" |IOSTANDARD = TMDS_33 ;
NET "hdmi_in_0_TMDS_pin(0)"  	LOC = "K17" |IOSTANDARD = TMDS_33 ; # Blue	
NET "hdmi_in_0_TMDSB_pin(0)"  LOC = "K18" |IOSTANDARD = TMDS_33 ;

NET "xps_iic_0_Scl"  LOC = "M16";
NET "xps_iic_0_Sda"  LOC = "M18";

NET "xps_iic_1_Scl_pin"  LOC = "C13" 
NET "xps_iic_1_Sda_pin"  LOC = "A13"

Should I  (is it safe to) modify constraint as follows :

NET "xps_iic_1_Scl_pin"  LOC = "C13" | IOSTANDARD=LVCMOS33 ;
NET "xps_iic_1_Sda_pin"  LOC = "A13" | IOSTANDARD=LVCMOS33 ;

Thank you for your advice !