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Receive CAT5 Ethernet signals directly into a PMOD port on a Basys3?


Is this insane?  Can I wire a PMOD port, specifically pins JA10 and JA4 as a differential receive port for a UDP project?

The brilliant guy who wrote this on fpga4fun.com built a circuit to generate a common mode input. If I attempt to wire RD+ and RD- directly to a differential pin pair in the PMOD port, am I wasting my time? Damaging my Basys3?  I'm thinking about starting by hooking it up with a project that is designed just to run an ILA and see what happens.  I am expecting these receive signals to be plus and minus 2.5v. I would like to wire those pins to an IBUFDS.

Please talk me out of this if I'm about to do something very stupid.  I fear I am about to embark on one of those "hold my beer" and "hey watch this" moments.

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Hi @FlyingBlindOnARocketCycle,

The short answer is no, you should not do this as is with the Basys 3.

The longer answer has multiple parts to it. One main drawback is that the Basys 3 does not have any dedicated differential pairs on our Pmod ports. There are some differential pairs on the XADC Pmod header, but those are limited between voltages of 0 and 1 V. Additionally, the Pmod host ports are connected to banks that are set at 3.3 V LVCMOS IO standard, which as per DS181 from Xilinx have absolute ranges of -0.300 V to 3.450 V, so you would damage the Basys 3 if you applied -2.5 V to a pin. I guess you could create a common-mode receiver circuit, but I don't know how well that would work.

For what it's worth though, no Digilent board that I am aware of has externally accessible differential pairs that can receive or output signals that are less than 0 V that doesn't have some sort of embedded transceiver built onto the board.


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The answer provided by @JColvinprobably should be sufficient. Before connecting external hardware to your FPGA pins make sure that signals driven into the pins are compatible and don't exceed input specifications. That's the place to start.

But as your project hopes are based on a project that seems to be based on another project.. none of which were completed, this should give you pause. The person who provided the HDL that was the basis of your coding efforts didn't seem to have much faith in his interface circuitry so why would you?

More to the point though is that if you don't understand how the circuitry operates and works then perhaps it's not ready to experiment with. More importantly, you should understand how, at least for 100Base-TX and above, Ethernet PHYs operate. Information on the physical layer for Ethernet is freely available. Do understand that Ethernet is a full duplex communications scheme and that on one end is a PHY driven through magnetics.

Both of the projects you alluded to are geared to 10BaseT Ethernet. You can have similar data rates using an FTxxxH USB UART bridge device at 8 or 12 Mbaud ( though sending binary data is a bit more complicated ). I understand the pleasures and intrigue of experimentation as an educational experiment but if you have a project that needs an Ethernet connection then there are simpler ways to go about it. One possibility is the PMODNIC100. This approach offers higher data rates and a simple SPI interface.

It's kind of amusing, in a way that brings a wince to your face, how someone posts an incomplete description of of an unfinished project that concentrates on one aspect of an idea and that gets partially consumed by someone else who posts about an unfinished project based on the first one, but concentrates on another aspect of the idea, with little attention to the other parts. And then later someone else decides to try it out without having verified if any of the parts are really ready for implementation.

I suppose that the title of the post, referencing CAT5 Ethernet signals, is more informative about the plausibility of design concept than you imagine.

Edited by zygot
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