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[Zybo z720] Integrate the External sensor and Pmod ESP32

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I have tried to use built-in xadc to acquire the analog sensor value. Now, I want to send my data from my analog sensor and other Pmod sensors to thingspeak through using Pmod ESP32. Here I find some trouble. In block design, there is always an implementation error. However, if I drop the ESP32 away from the block design, I can generate the bitstream, export to Vitis and get all the data in Vitis serial terminal. Next, I tried to integrate only the sensor and esp32 into one block design, it failed again.

I will show you the screenshot below for better illustration.  

I suspected the reason is the clock frequency and processor system reset. I hope any vivado genius can help my problem 

Screenshot (78).png

Screenshot (76).png

Screenshot (68).png

Screenshot (74).png

Screenshot (75).png

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Hi @lukelouyu,

I guess I am a bit confused; if you are able to get the pH and EC sensor working as expected with the xadc demo that you linked (which seems to be originally designed for the Zedboard for an older version of Vivado based on the screenshots used) and getting expected voltages after doing some conversions, I'm not certain what issue you are running into; just not being able to then generate the bitstream after adding more Pmods?

I'm not certain what problem you are seeing with the Peripheral I/O pins on the Zynq block reconfiguration screenshot; from what I can see it is the same as the Digilent block configuration that I have for the Zybo Z7-20 on Vivado 2019.2. One screenshot in the Lab3 document shows disabling Timer0 for the APU, but that is already done by default in the Digilent board files for the Zybo Z7-20. I'm guessing they needed to do it in the tutorial because the tutorial creators were using a different set of board files for the Zedboard and didn't have the Zynq IP pre-configured as needed.

I don't have all of the Pmods with me while working from home to test anything, but I did the following steps to get a bitstream and successfully reporting data received by the xadc (which Pmod JA) is attached to on a serial terminal in Vivado 2019.2

  • Add Zynq IP to new empty block design and run block automation with board preset
  • Double click on Zynq IP to add a second PL Fabric clock (FCLK_CLK1) at 100 MHz for the Pmod ESP32
  • From the board tab, add in the different Pmods to their connectors (ALS JB, AQS JC, HYGRO JD, ESP32 JE) but not clicking run connection automation.
  • Add in XADC wizard IP. Double click on the IP to reconfigure the defaults to enable Channel Sequencer and have vauxp6, 7, 14, and 15 enabled and vp/vn disabled.
  • Make Vauxp# and Vauxn# on the XADC wizard IP external.
  • Run Connection Automation. Make sure to have three clock sources (master, slave, and bridge if I recall the names correctly) for both the GPIO and UART AXI interfaces on the Pmod ESP32 be set to the 100 MHz clock in the pop-up where you select which things you want to automate. I left all of the other connections to be default, but you can specify for them to use the default 50 MHz fabric clock.
  • Validate the design, acknowledge the messages on negative DQS skews, and create a wrapper.
  • In the sources tab, add a constraints file with the following details:
    set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { vauxp14_0 }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p           
    set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { vauxp7_0 }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P             
    set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { vauxp15_0 }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P            
    set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { vauxp6_0 }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P             
    set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { vauxn14_0 }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N        
    set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { vauxn7_0 }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N             
    set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { vauxn15_0 }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N            
    set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { vauxn6_0 }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
  • Generate a bitstream and export the xsa including the bitstream

I kept getting various errors on the Vitis side of things with the xadc so I haven't gotten to debug those, but if you are able to reliably use the xadc code you posted, adding in other Pmods to the associated block design should in theory be more straightforward. I'll keep looking into it tomorrow.


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Hi @lukelouyu,

What specific errors is Vivado giving you when you attempt to add in the ESP32 IP?

I don't know how you have external sensor set up, but I was able to successfully generate a bitstream for a basic zynq design for the Zybo Z7-20 that uses the xadc wizard and the Pmod ESP32 IP on JE.



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Thanks for your answer. The error is implementation error. I can see that the difference between your block diagram and my block diagram is I add the external port for Vp_vn, Vaux7 and Vaux 14. And I set up 100MHz frequency for the Pmod ESP32. For set up, I connect my analog pH sensor signal pin into the the voltage regulating circuit. Then, I make a connection between the Zybo port Port A AD14 and the end side of the voltage regulating circuit. If I only insert the xadc wizard into the block diagram, the bitstream can be generated and I can receive the induced voltage of the sensor. Through setting the formula in the Vitis, I can get the pH value from my sensor. Now, I want to upload my sensor value to the thingspeak.

Previously, I have uploaded the temperature value, humidity value, ambient light value and carbon dioxide value into the thingspeak. If this problem solve, I can see all the value i needed in the thingspeak. 

I will show you some of the work I have done before this problem occured. 

This is how I set up for my xadc










This is how I set up for other Pmod sensor. 


The implementation error occurred when I tried to integrate these two things together. 

Here is error message

[Place 30-372] Bank 35 has terminals with incompatible standards:
Incompatible Pair of IO Standards: (IN of IO Standard LVCMOS18) & (INOUT of IO Standard LVCMOS33) have incompatible Vccs
 The following  terminals correspond to these IO Standards:
SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  In   Bank: 35 Placed :
    Term: Vaux14_0_v_n
    Term:  Vaux14_0_v_p
    Term:  Vaux7_0_v_n
    Term:  Vaux7_0_v_p
SioStd: LVCMOS33   VCCO = 3.3 Termination: 0  TermDir:  BiDi Bank: 35 Drv: 12 Placed :
    Term:  je_pin3_io
    Term:  and je_pin4_io

[Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

|                                                                     IO Placement : Bank Stats                                                                           |
| Id | Pins  | Terms |                               Standards                                |                IDelayCtrls               |  VREF  |  VCCO  |   VR   | DCI |
|  0 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 13 |    25 |     8 | LVCMOS33(8)                                                            |                                          |        |  +3.30 |    YES |     |
| 34 |    50 |    22 | LVCMOS33(22)                                                           |                                          |        |  +3.30 |    YES |     |
| 35 |    50 |     6 | LVCMOS18(4)  LVCMOS33(2)                                               |                                          |        |  +3.30 |    YES |     |
|    |   125 |    36 |                                                                        |                                          |        |        |        |     |

IO Placement:
| BankId |             Terminal | Standard        | Site                 | Pin                  | Attributes           |
| 13     | jb_pin10_io          | LVCMOS33        | IOB_X0Y5             | W6                   |                      |
|        | jb_pin1_io           | LVCMOS33        | IOB_X0Y20            | V8                   |                      |
|        | jb_pin2_io           | LVCMOS33        | IOB_X0Y19            | W8                   |                      |
|        | jb_pin3_io           | LVCMOS33        | IOB_X0Y28            | U7                   |                      |
|        | jb_pin4_io           | LVCMOS33        | IOB_X0Y27            | V7                   |                      |
|        | jb_pin7_io           | LVCMOS33        | IOB_X0Y24            | Y7                   |                      |
|        | jb_pin8_io           | LVCMOS33        | IOB_X0Y23            | Y6                   |                      |
|        | jb_pin9_io           | LVCMOS33        | IOB_X0Y6             | V6                   |                      |
| 34     | jc_pin10_io          | LVCMOS33        | IOB_X1Y95            | U12                  |                      |
|        | jc_pin1_io           | LVCMOS33        | IOB_X1Y80            | V15                  |                      |
|        | jc_pin2_io           | LVCMOS33        | IOB_X1Y79            | W15                  |                      |
|        | jc_pin3_io           | LVCMOS33        | IOB_X1Y98            | T11                  |                      |
|        | jc_pin4_io           | LVCMOS33        | IOB_X1Y97            | T10                  |                      |
|        | jc_pin7_io           | LVCMOS33        | IOB_X1Y84            | W14                  |                      |
|        | jc_pin8_io           | LVCMOS33        | IOB_X1Y83            | Y14                  |                      |
|        | jc_pin9_io           | LVCMOS33        | IOB_X1Y96            | T12                  |                      |
|        | jd_pin10_io          | LVCMOS33        | IOB_X1Y57            | V18                  |                      |
|        | jd_pin1_io           | LVCMOS33        | IOB_X1Y90            | T14                  |                      |
|        | jd_pin2_io           | LVCMOS33        | IOB_X1Y89            | T15                  |                      |
|        | jd_pin3_io           | LVCMOS33        | IOB_X1Y88            | P14                  |                      |
|        | jd_pin4_io           | LVCMOS33        | IOB_X1Y87            | R14                  | *                    |
|        | jd_pin7_io           | LVCMOS33        | IOB_X1Y78            | U14                  |                      |
|        | jd_pin8_io           | LVCMOS33        | IOB_X1Y77            | U15                  |                      |
|        | jd_pin9_io           | LVCMOS33        | IOB_X1Y58            | V17                  |                      |
|        | je_pin10_io          | LVCMOS33        | IOB_X1Y85            | Y17                  |                      |
|        | je_pin1_io           | LVCMOS33        | IOB_X1Y92            | V12                  |                      |
|        | je_pin2_io           | LVCMOS33        | IOB_X1Y63            | W16                  |                      |
|        | je_pin7_io           | LVCMOS33        | IOB_X1Y93            | V13                  |                      |
|        | je_pin8_io           | LVCMOS33        | IOB_X1Y81            | U17                  |                      |
|        | je_pin9_io           | LVCMOS33        | IOB_X1Y60            | T17                  |                      |
| 35     | Vaux14_0_v_n         | LVCMOS18        | IOB_X1Y107           | N16                  |                      |
|        | Vaux14_0_v_p         | LVCMOS18        | IOB_X1Y108           | N15                  |                      |
|        | Vaux7_0_v_n          | LVCMOS18        | IOB_X1Y105           | L15                  |                      |
|        | Vaux7_0_v_p          | LVCMOS18        | IOB_X1Y106           | L14                  |                      |
|        | je_pin3_io           | LVCMOS33        | IOB_X1Y100           | J15                  |                      |
|        | je_pin4_io           | LVCMOS33        | IOB_X1Y112           | H15                  |                      |


[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances


















Edited by lukelouyu
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Hi @lukelouyu,

I got the opportunity to look into this more and it seems like you are attempting to assign the vaux pins with a 1.8 V LVCMOS standard to an FPGA bank that is set at the 3.3 V LVCMOS standard. How did you define them in your .xdc file?

I hadn't actually connected a 100 MHz clock to my ESP32 IP block, but I recreated the design from scratch (still without manually assigning pins to the xadc wizard since you were able to generate a bitstream and get data from the pH sensor) properly connecting the 100 MHz to ESP32 and the default 50 MHz clock fabric clock for the rest of the IPs.

I have attached a .tcl to create the block design that I was able to create a bitstream for.



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Posted (edited)

Hi, @JColvin

Thanks you for answer me the question. In actually, I have done the similar block design with the block design you have sent to me. It can successfully generated the bistream, but when I insert my xadc code into the Vitis, let my zybo board to run the program and connect my pH sensor to the zybo baord, the zybo board cannot sense the induced voltage of the sensor. (I think the reason is I never make my xadc vaux14 and vaux7 to external. when I make these two to external, my zybo board can sense the voltage). Regarding to the question you asked me, I never use the xadc file for the block diagram. 

For xadc part, i used this tutorial (actually it is from another post in the FPGA forum) as guide. This tutorial does not need to use the xdc file. My pH sensor and EC sensor works in this diagram. ( I received the induced voltage from the sensor, after that I compared the pH value in Arduino and the induced voltage shown in Vitis Serial Terminal and get the formula to convert the induced voltage to the real pH value) 

 From here, i try to add another sensors like Pmod ESP32 and Pmod ALS etc, so that I can upload my pH sensor data to the Thingspeak. 

I will also provide you with the Vitis C code for xadc portion. 

Xadc Code.txt

I also realized this issue after I troubleshoot this block diagram. I am not sure if I can use this function to allow me generating the bistream sucessfully. 


In actually, I am also considering to use Pmod AD1 as a substitution to the built-in XADC since I can generate bistream with Pmod AD1 and Pmod ESP32. However, i need to wait for few days to receive my pmod ad1.  If you are okay, can you give me some suggestions on pmod ad1 as well. 





Edited by lukelouyu
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Posted (edited)


Thanks so much for your help. I can generate my bistream and export my xsa file into Vitis. I run my sample xadc code and it works! Now, I also can manage to upload my pH data into Thingspeak. Now, it is some small issue of inaccurate sensor result, but that is not about the fpga issue. 

Edited by lukelouyu
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