HLS project: GPIO to Master AXI only works with 1 out of 8 input ports

[rt54321]

I have a mostly working HLS and Zynq project, where the custom HLS block takes in 8 16-bit values (from external ADCs) and then transmit these 8 values to a DDR memory location.  Right now, I have dummy constants as the 8 inputs for testing:

Now, when I trigger the VIO (connected to the "go_flag"), I DO get an AXI memory transfer, but it transfers the decimal value "11" across all 8 memory locations:

So the first constant value is working, but the next seven are copies of the first.  Is this some kind of HLS "optimization" or caching problem?  I'm not sure why this is.  Here is my HLS code attached (I tried to keep it as simple as possible):

#include <stdint.h>
#include <ap_int.h>

#define NUM_ADC_SAMPLES		8

int AD7606_TO_MAXI_RMT(
			 volatile	int16_t 				adc_in1,
			 volatile	int16_t 				adc_in2,
			 volatile	int16_t 				adc_in3,
			 volatile	int16_t 				adc_in4,
			 volatile	int16_t 				adc_in5,
			 volatile	int16_t 				adc_in6,
			 volatile	int16_t 				adc_in7,
			 volatile	int16_t 				adc_in8,
			 volatile   uint32_t     			maxi_to_DDR[NUM_ADC_SAMPLES],
			 volatile   bool                 	go_flag,
			 volatile   int16_t					*counter_inner,
			 volatile   int16_t					*counter_outter)
{
#pragma HLS INTERFACE m_axi port=maxi_to_DDR offset=slave bundle=gmem
#pragma HLS INTERFACE ap_none  port=adc_in1
#pragma HLS INTERFACE ap_none  port=adc_in2
#pragma HLS INTERFACE ap_none  port=adc_in3
#pragma HLS INTERFACE ap_none  port=adc_in4
#pragma HLS INTERFACE ap_none  port=adc_in5
#pragma HLS INTERFACE ap_none  port=adc_in6
#pragma HLS INTERFACE ap_none  port=adc_in7
#pragma HLS INTERFACE ap_none  port=adc_in8
#pragma HLS INTERFACE ap_none  port=go_flag
#pragma HLS INTERFACE ap_none  port=counter_inner
#pragma HLS INTERFACE ap_none  port=counter_outter
#pragma HLS INTERFACE s_axilite port=return
	static int16_t counter_inner_local=0;
	static int16_t counter_outter_local=0;
	static uint8_t state_machine = 0;

	switch (state_machine)
	{
		case 0:
			if (go_flag == true)  state_machine = 1;
			break;
		case 1:
			if (go_flag == false) state_machine = 2;
			break;
		case 2:
			maxi_to_DDR[0] = adc_in1;
			maxi_to_DDR[1] = adc_in2;
			maxi_to_DDR[2] = adc_in3;
			maxi_to_DDR[3] = adc_in4;
			maxi_to_DDR[4] = adc_in5;
			maxi_to_DDR[5] = adc_in6;
			maxi_to_DDR[6] = adc_in7;
			maxi_to_DDR[7] = adc_in8;
			counter_inner_local++;
			state_machine = 0;
			break;
		default:
			state_machine = 0;
			break;
	}
	counter_outter_local++;
	*counter_inner=counter_inner_local;
	*counter_outter=counter_outter_local;
	return 0;
}

 

 

[Niță Eduard]

Hello,
Sorry for the late reply.
Perhaps using a pipeline directive to write the data in burst mode may fix the issue. Take a look at these code snippets.
I'm not sure how HLS will handle the switch statement, but from the page linked above it states that:

Quote

When using a for loop to implement burst reads or writes, follow these requirements:

• Pipeline the loop
• Access addresses in increasing order
• Do not place accesses inside a conditional statement
• For nested loops, do not flatten loops, because this inhibits the burst operation

So an issue may also be caused by this.
Maybe try to only send the data without the switch statement and see if the constants are sent correctly.

Best wishes,
Eduard