Recommended Posts


I would like to share a CMod S6 System on a Chip (S6 SoC) design.  This project is designed to demonstrate how capable a CMod-S6 can be, while also demonstrating a home-grown soft-core CPU: the Zip CPU.

In particular, the S6 SoC project demonstrates:

In the spirit of Free and Open Source, all of the source code for the project is available on OpenCores.



Link to post
Share on other sites
  • 9 months later...

For those interested ...

The project has since been moved from OpenCores to GitHub.  (I was unable to update the OpenCores repository.)  The ZipCPU on board now supports 8-bit byte accesses (as opposed to 32-bit bytes), a divide unit, and a much faster approach to reading from the flash (80MHz flash clock, 80MHz CPU clock).  As a result, the CPU should be able to execute one instruction every 17 clocks when running from the flash vice 52 clocks per instruction before.

If nothing else, this proves that with a little creativity, you can do a lot with a very minimalist board.


P.S. The CPU can nominally run at nearly one clock per instruction at 100MHz, but that requires a faster FPGA and enough logic to place an instruction cache on board.

Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now