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Does QSPI support legacy SPI devices?


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Hello, I want to use the Cmod-A7 for a project, but it uses the Microblaze processor and only supports QSPI, from what I can tell.

Is it possible to configure the QSPI port to use only part of its resources to drive a regular (legacy) SPI port?

Thank you, Richard V

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Hi @RichardV

Could you clarify what you mean by "the QSPI port"?

You can create your own SPI controller and have it use any of the Cmod's IO pins - constraining the pins with an XDC instead of through the board files. The AXI QSPI IP can similarly be connected to various external pins, on the Pmod port, breadboard connector, pretty much wherever (but should be used with a Microblaze processor). You can configure the AXI QSPI to work in standard SPI mode (SPI Options: Mode = Standard instead of Quad).

Thanks,

Arthur

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11 hours ago, RichardV said:

it uses the Microblaze processor and only supports QSPI

I'm not sure why you think that.

Can you provide a brief description of what you want to do in your project? For a small FPGA like the CMOD-A7 it certainly seems like a waste of resources to use a MicroBlaze processor. Of course it depends on what you want to do.

 

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Hello artvvb. Thank you for your response. I'm sorry if used the terms incorrectly. I meant that the Microblaze supports QSPI devices, but I only want to drive a simple SPI device, like an OLED or a temperature sensor. 

From what I recall, QSPI uses 4 lines for each of the MISO and MOSI signals.

It looks like you answered my question, the QSPI can be configured to run in "standard mode". It's unfortunate, though, that every example of the QSPI port uses all 4 lines to read a flash memory. 

I have sample projects for the OLED that use the ordinary SPI port, but it's for the Zynq. I want to use the Cmod-a7 for it's size, cost and form factor, but it uses the Microblaze. Is there any example that shows how to use the QSPI port in standard mode, or can you recommend what I should read?

Thank you, Richard V

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If the Zynq sample uses the AXI QSPI IP core, the software sources should nearly work as-is on Microblaze (typically with some additional calls to enable/disable caches if you are using them). If it's using the PS SPI instead, then that's different.

For a relatively simple case of using the AXI QSPI, you can take a look at the drivers for the Pmod AD5 IP:

https://github.com/Digilent/vivado-library/blob/master/ip/Pmods/PmodAD5_v1_0/drivers/PmodAD5_v1_0/examples/main.c

https://github.com/Digilent/vivado-library/blob/master/ip/Pmods/PmodAD5_v1_0/drivers/PmodAD5_v1_0/src/PmodAD5.c

https://github.com/Digilent/vivado-library/blob/master/ip/Pmods/PmodAD5_v1_0/drivers/PmodAD5_v1_0/src/PmodAD5.h

The following configuration should be good enough for a lot of devices, given the correct external clock, and use of the drivers. Chapter 4 (starting on page 87) of the Xilinx product guide for the core has some more info on how to configure it, which is linked from its product page: https://www.xilinx.com/products/intellectual-property/axi_quadspi.html.

-Arthur

image.thumb.png.f57d85d7432c8c8c8a6946c479e9046f.png

 

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Hello artvvb. Thank you for code, but I can't even generate a bitstream yet. Attached is my block diagram (without the GPIO signals for controlling the OLED). Did I do a simple error here? 

I keep getting weird errors even though I'm letting Vivado do the automated connecting. The messages are confusing and long (image below). All I want to is drive the PMOD OLED as a simple SPI port device. I managed to set the QSPI to Standard mode, Master, with FIFO enable (tried without FIFO too), but it still doesn't work. 

I cannot find a simple SPI example anywhere at Digilent that works with Microblaze; please prove me wrong if I am. Based on recent experience, the Zynq is not a good example to follow trying to program the Microblaze; it's just too confusing and many of the signals don't compare. For example, the Zynq SPI port has a slave select (SS) input that requires a constant to be applied as an input. Does the Microblaze have this same weird requirement? 

Is there a "document" (User Guide) that I can follow to set up the SPI port in Microblaze? I found this one (https://www.xilinx.com/support/documentation/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf), but it's not helpful with the setup in Vivado.

I can't even get the Nexys 4 Vivado example for the OLED example to compile (found here: https://reference.digilentinc.com/reference/pmod/pmodoled/start?redirect=1); the program says that "IP" structures are out of date, or I'm not allowed to use it for some reason. I keep running into examples that don't compile and this is extremely frustrating to those of us trying to LEARN. And Vivado keeps changing, so the help files get confusing when they deviate from the actual Vivado environment. 

Is there ANY OLED or "standard SPI" example (that isn't a flash memory example using QSPI) that actually works? I saw a link to some Github code written by some 3rd party, but the documentation is very poor and doesn't work without correcting all sorts of problems.

I'd be happy just to see a very simple SPI example using the Quad SPI. There are TOO many Zynq examples that are of no help with Microblaze. Any SPI device would be good, so long as it isn't a Zynq example.

This is my constraint file:

# Pmod Header JA
set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { OLED_DC   }]; #OLED D/C IO_L5N_T0_D07_14 Sch=ja[1]
set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { OLED_RST  }]; #OLED RST IO_L4N_T0_D05_14 Sch=ja[2]
set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { OLED_VBAT }]; #OLED VBAT IO_L9P_T1_DQS_14 Sch=ja[3]
set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { OLED_VDDC }]; #OLED VDDC IO_L8P_T1_D11_14 Sch=ja[4]
set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { OLED_CS[0]   }]; #OLED CS IO_L5P_T0_D06_14 Sch=ja[7]
set_property -dict { PACKAGE_PIN H19   IOSTANDARD LVCMOS33 } [get_ports { OLED_MOSI }]; #OLED MOSI IO_L4P_T0_D04_14 Sch=ja[8]
set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS33 } [get_ports { OLED_MISO }]; #OLED MISO IO_L6N_T0_D08_VREF_14 Sch=ja[9]
set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { OLED_SCK  }]; #OLED SCK IO_L8N_T1_D12_14 Sch=ja[10]
 

This is my block diagram that doesn't generate a bitstream.

image.thumb.png.c2fcb40626582304b44f5ade2d499fcc.png

These are the error messages: 

image.thumb.png.00d52d5176c3b2d4290ef975f44d8640.png

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Here's the mentioned example, connecting the Pmod OLED to the Cmod A7 through the Pmod port. Notably, the project uses the Pmod bridge IP to connect the QSPI to a board interface. Drivers are pulled from the IP core for the Pmod OLED. The Vitis workspace can be opened by importing projects from the .ide.zip file. 

Some screenshots of the section of interest of the block design and IP configurations are also attached, in case the tool version doesn't allow the project to be opened.

-Arthur

21582.xpr.zip cmod-a7-pmod-oled.ide.zip bd-screenshots.zip

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