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[Zybo Z720 Troubleshooting] Connect Two Pmods into One Zybo Z720 Pmod Port


helloworld1029

Question

Hi to everyone here.

I am constantly searching on connect two Pmods into one port. I have tried on "IOXP method" and "Daisy Chain Method", but I failed to achieve these two. After that, I found this post to tell me how to connect my two Pmods into one port.

The link is here: 

I followed the post instruction carefully. And I successfully create the Vivado Block Design, as well as generate the bistream. I wrote my C code based on the demo code of Pmod AQS and Pmod ALS. 

Here is the block diagram and the xdc file 

image.thumb.png.80ec71f095306bf5a53032fbcf7d579d.png

 

image.thumb.png.8dd1bbbf2a0ff791811f7d42bde2676a.png

After exporting to Vitis, I can successfully build my code. But the Vitis Serial Terminal said "Init Started" only, I think the new code failed to initialize two Pmods. I will place my code below. 

 

image.thumb.png.ca2b8bc5d497cc2fc694c7d672a81b0f.png

 

I also tried to place two different Pmod into two different ports, it works smoothly as the real data can be seen in the Vitis serial terminal. 

 

image.thumb.png.a50f139bd1021d742f0a53d3d71a5776.png

 

I wish anyone can help to troubleshoot my code and correct me if one of my step is wrongly done. Thanks in advance. 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Combine Test Code.txt

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Hi @helloworld1029

Currently your hardware design can only handle output. The Pmod IPs need to use tristate buffers. This is why each of the Pmod pins has an "_i", "_o", and "_t" port in the interface. Typically, the Pmod IP will handle this for you when working with the whole interface. Unfortunately, it looks like merely making the rest of the pins on the half of the interface you are working with external won't cause the buffers to be added. This means that you need to add the buffers manually. You can edit the HDL wrapper for your project, or you can try to work around it in the block design. I've provided a (partial) example of what the first method would look like below.

Thanks,

Arthur

 

Block design:

image.thumb.png.a7afcfea7094f827fb7c6070863e6108.png

 

Edited wrapper file:

//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov  6 21:40:23 MST 2019
//Date        : Wed Apr 28 11:39:43 2021
//Host        : WK142 running 64-bit major release  (build 9200)
//Command     : generate_target design_1_wrapper.bd
//Design      : design_1_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module design_1_wrapper
   (DDR_addr,
    DDR_ba,
    DDR_cas_n,
    DDR_ck_n,
    DDR_ck_p,
    DDR_cke,
    DDR_cs_n,
    DDR_dm,
    DDR_dq,
    DDR_dqs_n,
    DDR_dqs_p,
    DDR_odt,
    DDR_ras_n,
    DDR_reset_n,
    DDR_we_n,
    FIXED_IO_ddr_vrn,
    FIXED_IO_ddr_vrp,
    FIXED_IO_mio,
    FIXED_IO_ps_clk,
    FIXED_IO_ps_porb,
    FIXED_IO_ps_srstb,
    ja1,
    ja2,
    ja3,
    ja4
//    Pmod_out_pin1_i_0,
//    Pmod_out_pin1_o_0,
//    Pmod_out_pin1_t_0,
//    Pmod_out_pin2_i_0,
//    Pmod_out_pin2_o_0,
//    Pmod_out_pin2_t_0,
//    Pmod_out_pin3_i_0,
//    Pmod_out_pin3_o_0,
//    Pmod_out_pin3_t_0,
//    Pmod_out_pin4_i_0,
//    Pmod_out_pin4_o_0,
//    Pmod_out_pin4_t_0
    );
  inout [14:0]DDR_addr;
  inout [2:0]DDR_ba;
  inout DDR_cas_n;
  inout DDR_ck_n;
  inout DDR_ck_p;
  inout DDR_cke;
  inout DDR_cs_n;
  inout [3:0]DDR_dm;
  inout [31:0]DDR_dq;
  inout [3:0]DDR_dqs_n;
  inout [3:0]DDR_dqs_p;
  inout DDR_odt;
  inout DDR_ras_n;
  inout DDR_reset_n;
  inout DDR_we_n;
  inout FIXED_IO_ddr_vrn;
  inout FIXED_IO_ddr_vrp;
  inout [53:0]FIXED_IO_mio;
  inout FIXED_IO_ps_clk;
  inout FIXED_IO_ps_porb;
  inout FIXED_IO_ps_srstb;
  
  inout ja1;
  inout ja2;
  inout ja3;
  inout ja4;
//  input Pmod_out_pin1_i_0;
//  output Pmod_out_pin1_o_0;
//  output Pmod_out_pin1_t_0;
//  input Pmod_out_pin2_i_0;
//  output Pmod_out_pin2_o_0;
//  output Pmod_out_pin2_t_0;
//  input Pmod_out_pin3_i_0;
//  output Pmod_out_pin3_o_0;
//  output Pmod_out_pin3_t_0;
//  input Pmod_out_pin4_i_0;
//  output Pmod_out_pin4_o_0;
//  output Pmod_out_pin4_t_0;
  wire Pmod_out_pin1_i_0;
  wire Pmod_out_pin1_o_0;
  wire Pmod_out_pin1_t_0;
  wire Pmod_out_pin2_i_0;
  wire Pmod_out_pin2_o_0;
  wire Pmod_out_pin2_t_0;
  wire Pmod_out_pin3_i_0;
  wire Pmod_out_pin3_o_0;
  wire Pmod_out_pin3_t_0;
  wire Pmod_out_pin4_i_0;
  wire Pmod_out_pin4_o_0;
  wire Pmod_out_pin4_t_0;

  wire [14:0]DDR_addr;
  wire [2:0]DDR_ba;
  wire DDR_cas_n;
  wire DDR_ck_n;
  wire DDR_ck_p;
  wire DDR_cke;
  wire DDR_cs_n;
  wire [3:0]DDR_dm;
  wire [31:0]DDR_dq;
  wire [3:0]DDR_dqs_n;
  wire [3:0]DDR_dqs_p;
  wire DDR_odt;
  wire DDR_ras_n;
  wire DDR_reset_n;
  wire DDR_we_n;
  wire FIXED_IO_ddr_vrn;
  wire FIXED_IO_ddr_vrp;
  wire [53:0]FIXED_IO_mio;
  wire FIXED_IO_ps_clk;
  wire FIXED_IO_ps_porb;
  wire FIXED_IO_ps_srstb;
  wire Pmod_out_pin1_i_0;
  wire Pmod_out_pin1_o_0;
  wire Pmod_out_pin1_t_0;
  wire Pmod_out_pin2_i_0;
  wire Pmod_out_pin2_o_0;
  wire Pmod_out_pin2_t_0;
  wire Pmod_out_pin3_i_0;
  wire Pmod_out_pin3_o_0;
  wire Pmod_out_pin3_t_0;
  wire Pmod_out_pin4_i_0;
  wire Pmod_out_pin4_o_0;
  wire Pmod_out_pin4_t_0;

  design_1 design_1_i
       (.DDR_addr(DDR_addr),
        .DDR_ba(DDR_ba),
        .DDR_cas_n(DDR_cas_n),
        .DDR_ck_n(DDR_ck_n),
        .DDR_ck_p(DDR_ck_p),
        .DDR_cke(DDR_cke),
        .DDR_cs_n(DDR_cs_n),
        .DDR_dm(DDR_dm),
        .DDR_dq(DDR_dq),
        .DDR_dqs_n(DDR_dqs_n),
        .DDR_dqs_p(DDR_dqs_p),
        .DDR_odt(DDR_odt),
        .DDR_ras_n(DDR_ras_n),
        .DDR_reset_n(DDR_reset_n),
        .DDR_we_n(DDR_we_n),
        .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
        .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
        .FIXED_IO_mio(FIXED_IO_mio),
        .FIXED_IO_ps_clk(FIXED_IO_ps_clk),
        .FIXED_IO_ps_porb(FIXED_IO_ps_porb),
        .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
        .Pmod_out_pin1_i_0(Pmod_out_pin1_i_0),
        .Pmod_out_pin1_o_0(Pmod_out_pin1_o_0),
        .Pmod_out_pin1_t_0(Pmod_out_pin1_t_0),
        .Pmod_out_pin2_i_0(Pmod_out_pin2_i_0),
        .Pmod_out_pin2_o_0(Pmod_out_pin2_o_0),
        .Pmod_out_pin2_t_0(Pmod_out_pin2_t_0),
        .Pmod_out_pin3_i_0(Pmod_out_pin3_i_0),
        .Pmod_out_pin3_o_0(Pmod_out_pin3_o_0),
        .Pmod_out_pin3_t_0(Pmod_out_pin3_t_0),
        .Pmod_out_pin4_i_0(Pmod_out_pin4_i_0),
        .Pmod_out_pin4_o_0(Pmod_out_pin4_o_0),
        .Pmod_out_pin4_t_0(Pmod_out_pin4_t_0));
        
  assign Pmod_out_pin1_i_0 = ja1;
  assign ja1 = Pmod_out_pin1_t_0 ? Pmod_out_pin1_o_0 : 1'bz;
  assign Pmod_out_pin2_i_0 = ja2;
  assign ja2 = Pmod_out_pin2_t_0 ? Pmod_out_pin2_o_0 : 1'bz;
  assign Pmod_out_pin3_i_0 = ja3;
  assign ja3 = Pmod_out_pin3_t_0 ? Pmod_out_pin3_o_0 : 1'bz;
  assign Pmod_out_pin4_i_0 = ja4;
  assign ja4 = Pmod_out_pin4_t_0 ? Pmod_out_pin4_o_0 : 1'bz;
  
endmodule

 

 

Edited by artvvb
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