Missing timing constraints on custom pcore used as a clock generator ?

[chcollin]

Hi,

I'm trying to tune Atlys HDMI Demo project so that HDMI output delivers a pure 74.25 MHz 720p signal and not 75 MHz as actually designed.
To achevieve this goal, I designed a self made pcore to act as a clock generator.
This "720p compliant clock generator" pcore is a simple vhdl/mpd file.

Attached is a diagram of what this pcore does. Mainly it is supposedly using one sole CMT, implementing cascading two DCM_CLKGEN and one PLL_BASE.

The idea was to replace the original clock generator of the design with this core.
Instead of delivering 600Mhz and 75MHz outputs, it delivers 594MHz and 74.25MHz.

• 74.25MHz clock is intended to clock buses, microblaze, hdmi_out core
• 594MHz clocks are intended to clock MPMC core (8 times microblaze clocks).

Now for my questions ? :

1/ I am not so sure about the locked/rst chains I designed. Could anyone confirm it is correct or give me suggestions on how to make it good ?

2/ I can no longer use the clock wizard in XPS as I replaced the original clock generator with this core. If I try to launch Clock Wizard in XPS, it complains there is no clock generator core and tells me to add one from the IP Library. My question : is there a way I could "persuade" XPS that my core is a clock generator so that it can calculate and validate timings with this home made core ?

3/ Last (but not least) : the project does generate a bitstream. However I'm quite sure the whole timing part is not processed as it does not work. No signal from hdmi_out when using this core. The number of files produced during bitstream generation is awfully low (400 instead of more than 2300 when generating with original design). So I guess I must have missed something : probably the time constraints. The problem is that I have absolutely no idea where to begin with this as I have never ever coded timing constrains.. 

I would really appreciate any guidance on how to solve these problems. Cheers.

N.B : this is an XPS project under ISE 14.7.

[chcollin]

BTW, now J1 works fine, I managed to clock the whole system at 74.25 MHz !
It's been a long way, but finally made it !!!

Thanx @zygotfor all the help you gave and explanations, that helped me much in the understanding of my problem.

[zygot]

I like the idea of cascading DCMs.

You will not get ISE or Vivado Wizards to evaluate you own IP, so you will have to do this for yourself. I don't think that the Wizard even knows about cascaded DCM designs anyway.

You might be able to get an idea of the feasibility of your concept by trying to use the Wizard to create your clock outputs from the given input clock and see what it produces. Unfortunately, while the Spartan 6 device is still a great device it has inferior clocking capabilities than the more recent Series 7 devices. Getting an arbitrary clock out of any input clock can be problematic if jitter is of concern. 

The best approach might be to use an external programmable clock module, possibly with with another clock source. One feature lacking in the higher end Digilent FPGA platforms is a good programmable external clock source. This is a shame because cocking is critical to the success of many designs.

[chcollin]

Hi @zygot,

Thank your for your reply ?

I've read several times that cascading 2 DCMs is not advised by Xilinx, yet I wanted to give it a try...
The thing is I wanted to remain in one sole CMT as Atlys only has 4 of those ... so I couldnt figure out any other way to achieve my frequencies.

Clock wizard doesn't know about cascading DCMs, it only provides PLL and/or DCM, eventually cascaded (DCM2PLL or PLL2DCM).

I've tried using the clock wizard, but of course it can't produce my desired frequencies, this is the reason why I had to make "a clock generator on my own". 

I would love to add a 74.25Mhz clock oscilator board to the Atlys, but I'm not sure this is possible. If someone at Digilet reads this, can you point me to such hardware option ?

Yet, the question remains :
With adapted time constraints in my UCF, wouldn't it possible to have the project generate good clocks scheme ?

Cheers

EDIT : I might post logs of project generation, maybe that would help see what's wrong and frequencies produced ?

Edited April 19, 2021 by chcollin

[chcollin]

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|clock_generator_720p |              |      |      |            |             |
|           _0_CLKOUT |  BUFGMUX_X2Y2| No   | 2175 |  0.682     |  2.391      |
+---------------------+--------------+------+------+------------+-------------+
|hdmi_out_0_VFBC_OUT_ |              |      |      |            |             |
|             cmd_clk | BUFGMUX_X3Y14| No   |  107 |  0.060     |  1.769      |
+---------------------+--------------+------+------+------------+-------------+
|hdmi_in_0_VFBC_OUT_c |              |      |      |            |             |
|              md_clk |  BUFGMUX_X2Y4| No   |  434 |  0.666     |  2.374      |
+---------------------+--------------+------+------+------------+-------------+
|hdmi_in_0_VFBC_OUT_w |              |      |      |            |             |
|               d_clk | BUFGMUX_X2Y12| No   |   84 |  0.184     |  1.893      |
+---------------------+--------------+------+------+------------+-------------+
|microblaze_0_mdm_bus |              |      |      |            |             |
|            _Dbg_Clk | BUFGMUX_X2Y10| No   |   64 |  0.060     |  1.770      |
+---------------------+--------------+------+------+------------+-------------+
|pll_module_0_CLKOUT2 |              |      |      |            |             |
|                     |  BUFGMUX_X2Y1| No   |   25 |  0.363     |  2.081      |
+---------------------+--------------+------+------+------------+-------------+
|hdmi_in_0/hdmi_in_0/ |              |      |      |            |             |
|USER_LOGIC_I/Inst_dv |              |      |      |            |             |
|   i_decoder/pclkx10 |         Local|      |   12 |  0.038     |  1.560      |
+---------------------+--------------+------+------+------------+-------------+
|hdmi_out_0/hdmi_out_ |              |      |      |            |             |
|0/Inst_dvi_out_nativ |              |      |      |            |             |
|           e/pclkx10 |         Local|      |    8 |  0.000     |  1.740      |
+---------------------+--------------+------+------+------------+-------------+
|MCB_DDR2/MPMC_Clk_Me |              |      |      |            |             |
|   m_2x_180_bufpll_o |         Local|      |   37 |  0.723     |  1.570      |
+---------------------+--------------+------+------+------------+-------------+
|MCB_DDR2/MPMC_Clk_Me |              |      |      |            |             |
|       m_2x_bufpll_o |         Local|      |   34 |  0.704     |  1.551      |
+---------------------+--------------+------+------+------------+-------------+
|MCB_DDR2/MCB_DDR2/mp |              |      |      |            |             |
|mc_core_0/gen_sparta |              |      |      |            |             |
|n6_mcb.s6_phy_top_if |              |      |      |            |             |
|/mpmc_mcb_raw_wrappe |              |      |      |            |             |
|     r_0/ioi_drp_clk |         Local|      |   22 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
|microblaze_0_mdm_bus |              |      |      |            |             |
|         _Dbg_Update |         Local|      |   21 |  4.121     |  6.327      |
+---------------------+--------------+------+------+------------+-------------+
|MCB_DDR2/MCB_DDR2/mp |              |      |      |            |             |
|mc_core_0/gen_sparta |              |      |      |            |             |
|n6_mcb.s6_phy_top_if |              |      |      |            |             |
|/mpmc_mcb_raw_wrappe |              |      |      |            |             |
|r_0/idelay_dqs_ioi_s |              |      |      |            |             |
|                     |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
|MCB_DDR2/MCB_DDR2/mp |              |      |      |            |             |
|mc_core_0/gen_sparta |              |      |      |            |             |
|n6_mcb.s6_phy_top_if |              |      |      |            |             |
|/mpmc_mcb_raw_wrappe |              |      |      |            |             |
|r_0/idelay_dqs_ioi_m |              |      |      |            |             |
|                     |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
|MCB_DDR2/MCB_DDR2/mp |              |      |      |            |             |
|mc_core_0/gen_sparta |              |      |      |            |             |
|n6_mcb.s6_phy_top_if |              |      |      |            |             |
|/mpmc_mcb_raw_wrappe |              |      |      |            |             |
|r_0/idelay_udqs_ioi_ |              |      |      |            |             |
|                   s |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+
|MCB_DDR2/MCB_DDR2/mp |              |      |      |            |             |
|mc_core_0/gen_sparta |              |      |      |            |             |
|n6_mcb.s6_phy_top_if |              |      |      |            |             |
|/mpmc_mcb_raw_wrappe |              |      |      |            |             |
|r_0/idelay_udqs_ioi_ |              |      |      |            |             |
|                   m |         Local|      |    1 |  0.000     |  0.002      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Number of Timing Constraints that were not applied: 6

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_clock_generator_720p_0_CLKOUT8X180 = P | MINPERIOD   |     0.084ns|     1.599ns|       0|           0
  ERIOD TIMEGRP         "clock_generator_72 |             |            |            |        |            
  0p_0_CLKOUT8X180"         TS_clock_genera |             |            |            |        |            
  tor_720p_0_clock_generator_720p_0_dcm1_cl |             |            |            |        |            
  kfx * 8 PHASE         0.841750842 ns HIGH |             |            |            |        |            
   50% |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clock_generator_720p_0_CLKOUT8X = PERI | MINPERIOD   |     0.084ns|     1.599ns|       0|           0
  OD TIMEGRP         "clock_generator_720p_ |             |            |            |        |            
  0_CLKOUT8X"         TS_clock_generator_72 |             |            |            |        |            
  0p_0_clock_generator_720p_0_dcm1_clkfx *  |             |            |            |        |            
  8 HIGH         50% |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clock_generator_720p_0_clock_generator | SETUP       |     1.212ns|    12.256ns|       0|           0
  _720p_0_pll0_clkout2 = PERIOD TIMEGRP     | HOLD        |     0.210ns|            |       0|           0
       "clock_generator_720p_0_clock_genera |             |            |            |        |            
  tor_720p_0_pll0_clkout2"         TS_clock |             |            |            |        |            
  _generator_720p_0_clock_generator_720p_0_ |             |            |            |        |            
  dcm1_clkfx HIGH 50% |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clock_generator_720p_0_clock_generator | MINLOWPULSE |     8.468ns|     5.000ns|       0|           0
  _720p_0_dcm1_clkfx = PERIOD TIMEGRP       |             |            |            |        |            
     "clock_generator_720p_0_clock_generato |             |            |            |        |            
  r_720p_0_dcm1_clkfx"         TS_clock_gen |             |            |            |        |            
  erator_720p_0_clock_generator_720p_0_dcm0 |             |            |            |        |            
  _clkfx * 3.3 HIGH         50% |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_pll_module_0_pll_module_0_CLKOUT2_BUF  | SETUP       |     1.506ns|     5.228ns|       0|           0
  = PERIOD TIMEGRP         "pll_module_0_pl | HOLD        |     0.320ns|            |       0|           0
  l_module_0_CLKOUT2_BUF"         TS_clock_ |             |            |            |        |            
  generator_720p_0_clock_generator_720p_0_p |             |            |            |        |            
  ll0_clkout2 * 2 HIGH         50% |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |     4.660ns|     5.340ns|       0|           0
  pin" 100 MHz HIGH 50% |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_pll_module_0_pll_module_0_CLKOUT1_BUF  | SETUP       |     4.753ns|     8.715ns|       0|           0
  = PERIOD TIMEGRP         "pll_module_0_pl | HOLD        |     0.248ns|            |       0|           0
  l_module_0_CLKOUT1_BUF"         TS_clock_ |             |            |            |        |            
  generator_720p_0_clock_generator_720p_0_p |             |            |            |        |            
  ll0_clkout2 HIGH         50% |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ramra_0 = MAXDELAY FROM TIMEGRP "bramr | SETUP       |     7.593ns|     5.875ns|       0|           0
  a_0" TO TIMEGRP "fddbgrp_0"         TS_pl | HOLD        |     0.898ns|            |       0|           0
  l_module_0_pll_module_0_CLKOUT1_BUF       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ramdo_0 = MAXDELAY FROM TIMEGRP "bramg | SETUP       |     8.183ns|     5.285ns|       0|           0
  rp_0" TO TIMEGRP "fddbgrp_0"         TS_p | HOLD        |     0.420ns|            |       0|           0
  ll_module_0_pll_module_0_CLKOUT1_BUF      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clock_generator_720p_0_clock_generator | MINLOWPULSE |    12.444ns|    32.000ns|       0|           0
  _720p_0_dcm0_clkfx = PERIOD TIMEGRP       |             |            |            |        |            
     "clock_generator_720p_0_clock_generato |             |            |            |        |            
  r_720p_0_dcm0_clkfx"         TS_sys_clk_p |             |            |            |        |            
  in * 0.225 HIGH 50% |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  PATH "TS_TIG_MCB_DDR2_S6_SYS_RST_SYNCH_pa | SETUP       |         N/A|     3.721ns|     N/A|           0
  th" TIG                                   |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_pll_module_0_CLKOUT0 = PERIOD TIMEGRP  | N/A         |         N/A|         N/A|     N/A|         N/A
  "pll_module_0_CLKOUT0"         TS_clock_g |             |            |            |        |            
  enerator_720p_0_clock_generator_720p_0_pl |             |            |            |        |            
  l0_clkout2 * 10         HIGH 50% |             |            |            |        |            
----------------------------------------------------------------------------------------------------------


Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_pin                 |     10.000ns|      5.340ns|      9.498ns|            0|            0|            0|       517996|
| TS_clock_generator_720p_0_cloc|     44.444ns|     32.000ns|     42.214ns|            0|            0|            0|       517996|
| k_generator_720p_0_dcm0_clkfx |             |             |             |             |             |             |             |
|  TS_clock_generator_720p_0_clo|     13.468ns|      5.000ns|     12.792ns|            0|            0|            0|       517996|
|  ck_generator_720p_0_dcm1_clkf|             |             |             |             |             |             |             |
|  x                            |             |             |             |             |             |             |             |
|   TS_clock_generator_720p_0_cl|     13.468ns|     12.256ns|     10.456ns|            0|            0|       498158|        19838|
|   ock_generator_720p_0_pll0_cl|             |             |             |             |             |             |             |
|   kout2                       |             |             |             |             |             |             |             |
|    TS_pll_module_0_pll_module_|     13.468ns|      8.715ns|      5.875ns|            0|            0|        19569|          150|
|    0_CLKOUT1_BUF              |             |             |             |             |             |             |             |
|     TS_ramdo_0                |     13.468ns|      5.285ns|          N/A|            0|            0|           30|            0|
|     TS_ramra_0                |     13.468ns|      5.875ns|          N/A|            0|            0|          120|            0|
|    TS_pll_module_0_CLKOUT0    |      1.347ns|          N/A|          N/A|            0|            0|            0|            0|
|    TS_pll_module_0_pll_module_|      6.734ns|      5.228ns|          N/A|            0|            0|          119|            0|
|    0_CLKOUT2_BUF              |             |             |             |             |             |             |             |
|   TS_clock_generator_720p_0_CL|      1.684ns|      1.599ns|          N/A|            0|            0|            0|            0|
|   KOUT8X180                   |             |             |             |             |             |             |             |
|   TS_clock_generator_720p_0_CL|      1.684ns|      1.599ns|          N/A|            0|            0|            0|            0|
|   KOUT8X                      |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
   constraint is not analyzed due to the following: No paths covered by this 
   constraint; Other constraints intersect with this constraint; or This 
   constraint was disabled by a Path Tracing Control. Please run the Timespec 
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.

 

[chcollin]

 

[zygot]

3 hours ago, chcollin said:

With adapted time constraints in my UCF, wouldn't it possible to have the project generate good clocks scheme ?

No. Timing constraints help the synthesis and P&R make good decisions about routing and placing logic, it can't magically select the best clocking scheme for you and implement it.

You can make a large number of DMC clock output frequencies from a given clock input frequency; the impacted variable is jitter. The ISE and Vivado clock wizards allow you to specify output jitter, so you can increase the odds of getting a frequency close to the desired one by relaxing the jitter spec. You can also just instantiate a DCM as a primitive and choose your own multiply/divide factors. This approach lets you select more ouput frequency possibilities...  but the burden of determining the quality of your final clock is up to you.

Again, the best way to get the clock frequency that you want is to add external hardware. The ATLYS has a VHDCI connector that supports this; at least 2 pin pairs are connected to clock capable FPGA IO pins. Also, JB shares signals with one of the PMODA HDMI connector and has a clock capable IO pair. You'll need to pay close attention to the bank IO Vccio and the external clock module output logic for compatibility.

Edited April 19, 2021 by zygot

[chcollin]

Thank you very much @zygot, your help is really appreciated.

If some personnel at Digilent reading this thread could give me advice or point me to such a piece of hardware, that would be fantastic !

To sum it up, I need a 74.25MHz external clock device compatible with Atlys, ideally VHDCI plugable, right ?

[zygot]

21 minutes ago, chcollin said:

To sum it up, I need a 74.25MHz external clock device compatible with Atlys, ideally VHDCI plugable, right ?

That's a tall order. Digilent made a few breadboard cards for the VHDC connectors on the ATLYS and original Genesys boards but they aren't ideal.

I think that your best bet is to use the PMOD connector and make your own external clock module card. If you go to Mouser (or convenient distributor for you ) and search for "74.25 MHz clock module" you will find a few 3.3V single-ended modules available. This would be the simplest way to go. Fortunately, your frequency isn't odd so there are possibilities. For sing;e-ended clock inputs you'll need to use the _p pin.

The only peripheral for the VHDC connector that I'm aware of from Digilent was a dual camera board... all in all this was mostly a dead end interface. It's also darn hard to work with using simple layout PCB software if you want to design your own add-on board. It's certainly caused me much frustration as I use both of those Digilent FPGA boards on a regular basis.

 

Edited April 19, 2021 by zygot

[chcollin]

Thank you very much @zygot for the time you spent on replying me, that's very nice of you.

Unfortunately, I'm afraid your solution is the way to go...
I say "unfortunately" because designing and making such a board is totally out of my field of skills !
Indeed, I am not into electronics at all, neither in the fpga thing as you might have understood from my naive questionnings :)

Let me try to find someone able to do this for me, I hope I'll find.

Once again, thank you very for all your replies, that led me to a clearer comprehension of my problem.

Cheers.

Edited April 20, 2021 by chcollin

[chcollin]

A last question @zygot, please.

In case I could not find some clock generator board to clock my atlys, and knowing that the HDMI D plug shares pins with the pmod plug, especially clock pins, what do you think of this :
Could I use some video device (for instance, some raspberry pi that I own), configured to display @720p and plugged into Atlys HDMI D port ?

Would this, in your opinion, provide a decent 74.25MHz system clock for my scheme ?

EDIT : I don't even know why bother use JA Type D HDMI plug, I could simply plug the raspberry into J3 Type A HDMI connector to get clock signals, couldn't I ?

Edited April 21, 2021 by chcollin

[zygot]

TMDS requires 50 termination to function.

The HDMI INput connector J3 uses the TMDS141 TMDS re-timer device to accomplish proper termination. You need to be careful with HDMI. Because of those 50 ohm terminators you end up with a path for external devices to pump current into the ATLAS Vccio rails... so the system power-up sequence is important. You don't want to drive current into the FPGA rails before the ATLYS board has been powered an it's own power rails are stable. Just connecting supply rails between two independently powered boards without carefeul current management is scary. Ideally, you'd have a switch that disconnects input TMDS terminators until the receiving board has powered on ( and in the case of the ALTYS the FPGA device has been configured ). This is an added expense that no FPGA development board, that I know of, with HDMI inputs is burdened with.  This is a real concern that needs to be addressed, and it's really an HDMI issue. Having said that it's conceivable that you could use J3 as an external clock source.... but of course there's no clock on the sink end before the external source is running... and you don't want the external TMDS driver running until the ATLYS is powered on... it's a dilemma.

I wouldn't advise using the JA mini-HDMI connector for HDMI connections as there is no proper TMDS termination on those signals. There are 50 ohm series resistors between JA and the JA-Dx and JA-CLKx signals into the FPGA, but not between JB and the same FPGA IO pins. The JA/JB connector pins go to IO bank 2 which happens to have a user-selectable Vccio of either 3.3V for single-ended signals or 2.5V for differential signals. Be aware that your choice of Vccio will affect every signal connected to IO bank 2 leading to potential conflicts ( you can't have conflicting IOSTANDARD constraints on the same bank ).

JB on the ATLYS is the only PMOD on a Digilent board ( as far as I'm aware of ) that has user configurable Vccio options. This makes it unique.

I don't see an easy, no effort, way to get you your preferred clock signal.  

Edited April 21, 2021 by zygot

[zygot]

It's kind of a shame that Digilent was historically so sloppy with their PMOD designs on the FPGA boards. Very few PMODs are connected to clock capable pins on the FPGA. A problem is the 12-pin connector... it really limits what you can do with it, and I think that the decision to double the GND and Vcc pins is generally not all that useful and certainly exacerbates the issue. A simple PMOD with holes for an external clock module would make the whole ecosystem better... but what's the point when almost none of the FPGA boards can make use of it?

I strongly advise Digilent to reconsider their product vision with respect to their unwavering commitment to the 6-pin 12-pin PMOD lock-in strategy. They still can support this ecosystem and make boards that suits their customers' interests at the same time... to me that's a win-win for everyone.

Edited April 21, 2021 by zygot

[zygot]

Since you are using the ATLYS I feel that it's appropriate to warn you about those USB Type-B plugs. The only thing holding them onto the board is a thin strip of copper on the mounting surface of the PCB. I've had about a 50% failure rate with these over repeated use; that is the connector, and copper signal traces being ripped off the board. One problem is that some of these have a fairly high insertion force requirement and the surface mount USB connectors just aren't up to the task over time. It isn't only cheap FPGA boards with the problem. I have a couple of 'not cheap' nVidia dev boards that are now useless. At least the ATLYS has a JTAG header as an alternate configuration method... which my ALTAS is now dependent on to be useful.

A generous dollop of non-conductive epoxy around the mounting tabs provides some added mechanical stability... if applied before there's a problem.

I'm always on the lookout for this kind of mistake by vendors... but really, there's no excuse for saving a few cents by using SMT USB connectors. Don't do it!

Edited April 21, 2021 by zygot

[chcollin]

On 4/21/2021 at 4:08 PM, zygot said:

I wouldn't advise using the JA mini-HDMI connector for HDMI connections as there is no proper TMDS termination on those signals. There are 50 ohm series resistors between JA and the JA-Dx and JA-CLKx signals into the FPGA, but not between JB and the same FPGA IO pins. The JA/JB connector pins go to IO bank 2 which happens to have a user-selectable Vccio of either 3.3V for single-ended signals or 2.5V for differential signals. Be aware that your choice of Vccio will affect every signal connected to IO bank 2 leading to potential conflicts ( you can't have conflicting IOSTANDARD constraints on the same bank ).

JB on the ATLYS is the only PMOD on a Digilent board ( as far as I'm aware of ) that has user configurable Vccio options. This makes it unique.

Thank you @zygot for all this explanations, that's very kind of you.
I guess you are talking about JP12 jumper to select Vccio for IO bank 2.

Lately, I've been working on acquiring hdmi signal on J1, but still unsuccessfully. As reported on this topic, i've been coding a core to act as an EDID emulator.
This core is simply a PLB master core. At initialization, it configures xps_iic PLB slave IP cores as a DDC slave (address 0x50) and then catches interrupts from xps_iic to write EDID information to the xps_iic registers that handles DDC/I2C protocol with the host.

Things work fine when xps_iic is attached to J3 I2C line (M16 and M18). However, I get no signal when attached to J1 I2C line (A13,C13).

In addition if I instantiate 2 xps_iic cores, one attached to J1 and the other to J3, plus attaching a core to J2 TMDS (output), I get this error message at bitstream generation :

Incompatible IOB's are locked to the same bank 0
   Conflicting IO Standards are:
   IO Standard 1: Name = TMDS_33, VREF = NR, VCCO = 3.30, TERM = NONE, DIR =
   OUTPUT, DRIVE_STR = NR
   List of locked IOB's:
   	hdmi_out_0_TMDS_pin<0>
   	hdmi_out_0_TMDS_pin<1>
   	hdmi_out_0_TMDS_pin<2>
   	hdmi_out_0_TMDS_pin<3>
   	hdmi_out_0_TMDSB_pin<0>
   	hdmi_out_0_TMDSB_pin<1>
   	hdmi_out_0_TMDSB_pin<2>
   	hdmi_out_0_TMDSB_pin<3>

   IO Standard 2: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
   BIDIR, DRIVE_STR = 12
   List of locked IOB's:
   	xps_iic_1_Sda
   	xps_iic_1_Scl

   These IO Standards are incompatible due to VCCO mismatch.

As you know the Atlys platform quite well, could you give me suggestion on :

• board jumpers configuration
• constraints needed

So that I can use all three HDMI ports without error ?

If needed, I can attach current UCF and jumpers conf.

Many thanks in advance if you can help me.
Regards

[chcollin]

OK, I finally managed to have J1 working following this document.

For archiving purpose, here's a picture of how jumpers should be set for using J1.
N.B : Although not documented in Atlys datasheet, JP5 MUST BE LOADED to enable J1.
Also, be careful with "J2", labelled SDA/SCL. Jumper must be set "horizontally".

[zygot]

35 minutes ago, chcollin said:

BTW, now J1 works fine, I managed to clock the whole system at 74.25 MHz !
It's been a long way, but finally made it !!!

Thanks for reporting your success as well as your problems. I'd have been happier to have been able to offer answers to more of your questions but it's been so long since I've use the ATLYS for video I'm not sure what PC those projects are on, and I didn't want to rely on memory. But, it's always better to see someone figure out solutions on their own anyway.