AXI peripheral controlling custom PMOD

[PoroCYon]

Hi,

First some context: I'm trying to make a flashcart-like device (acting like a game cartridge for a console) using a Zybo. For this I'd need to interface with the processing system on one side (to manage which data goes in and out, and also to control a weird bizarro UART on the console which uses a PS/2 port but the protocol is totally different), and the pmod interfaces on the other side (to read out address lines and control signals, and to drive the data lines and UART). (The console in question here is the V-tech V.smile. Yes.)

 

What would be the best way to create a custom IP in Vivado that accomplishes this? First create an AXI peripheral, then manually add the Pmod signals in the generated HDL code, and then group these into a Pmod interface in the "Ports and interfaces" UI? Or should I declare the signals in the constraints file, and then add them manually to the HDL wrapper etc. until it gets to my code? Or some other method?

If the former, I have a few followup questions: why do these Pmod interfaces have 10 signals, while this page tells me there are only 8 data pins, and 2 for VCC and GND each. Are two of these signals unused? What if I use a pmod pin in only one direction, do I just leave the other unconnected, or should I do something else? What are the singals with suffix "_t" for, exactly?

 

Thanks.

[artvvb]

Hi @PoroCYon, welcome to the forums!

An option that resembles the first you proposed: you can create an AXI peripheral with its ports either grouped into a GPIO interface or just on four-bit _i, _o, and _t buses, then use the Pmod Bridge IP from our vivado-library repo (latest released download here) to handle the constraints, connecting your IP to the bridge in a block design. I've attached a screenshot of how this could be wired up in the block design below (it uses an RTL module where your AXI IP would fit in).

Connecting a Pmod interface to a board-flow port requires some additional logic in the IP's GUI TCL scripts, which gets pretty messy - I recommend using the bridge instead.

Manually constraining your IP's external ports is also a good option (right click on a pin, select make external, then add it to the constraint file).

The _i, _o, and _t pins denote the three pins of a tristate buffer that gets implicitly added to the design between these pins and the physical FPGA pin. _t selects between input and output.

Thanks,

Arthur