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demo example of ETHERNET for the NEXYS A7


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Hi!

I would like to use the ETHERNET at NEXYS A7.

There is the description "An EDK demonstration project that properly uses the Ethernet PHY can be found on the Nexys A7 product page" In the reference manual of NEXYS A7, but I couldn't to find it.

Where can I find it?

 

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Hi @hiro_ike,

I looked for this EDK demo project that is mentioned, but have not been able to find it on any of the Nexys Resource Centers, so I'll make sure that line gets removed from the various reference manuals.

There is an old guide for getting a Microblaze server running on the Nexys 4 DDR (it's the same board as the Nexys A7, but without the newer branding) available here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze-servers/start.

Of note though is that later versions of Vivado (2019.2 and later if I recall correctly) no longer include the MII2RMII IP core and Xilinx does not have any replacement options for it, though you can potentially copy over the source files from earlier versions of Vivado into later versions. Both of these things are noted in this Xilinx forum thread.

Thanks,
JColvin

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On 4/16/2021 at 2:12 PM, JColvin said:

Hi @hiro_ike,

I looked for this EDK demo project that is mentioned, but have not been able to find it on any of the Nexys Resource Centers, so I'll make sure that line gets removed from the various reference manuals.

There is an old guide for getting a Microblaze server running on the Nexys 4 DDR (it's the same board as the Nexys A7, but without the newer branding) available here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze-servers/start.

Of note though is that later versions of Vivado (2019.2 and later if I recall correctly) no longer include the MII2RMII IP core and Xilinx does not have any replacement options for it, though you can potentially copy over the source files from earlier versions of Vivado into later versions. Both of these things are noted in this Xilinx forum thread.

Thanks,
JColvin

I tried running the "old guide" on a Nexys A7 and there is a problem with step 3.1 : The IP "Ethernet PHY MII to Reduced MII" is not a menu selection

--------------------------------------

3.1) We will now add all of the necessary IP blocks to our project. There are 4 cores we will add:

* Memory Interface Generator

* Ethernet PHY MII to Reduced MII  <<< ------ DOES NOT EXIST IN THE IP MENU

* AXI Uartlite * AXI EthernetLite

* AXI Timer

--------------------------------------

What is the workaround for this? (I tried adding some of the other ethernet IP from the menu and they did not work.)

Is there a tutorial (that works) to demonstrate the NEXYS A7 Ethernet IP?

    - I have spent many hours trying to get this to work.

    - I tried adapting this YouTube tutorial without success: https://www.youtube.com/watch?v=QhTYsysSkB0&t=1246s

My thanks in advance for any suggestions.

Curtis

 

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Hello @CurtisNotestine,

What version of Vivado are you using? Xilinx no longer includes, and has no plans for replacing the Ethernet PHY MII to Reduced MII (MII2RMII) in versions 2019.2 or later. The current work around is to obtain a copy of the IP provided in Vivado 2019.1 or earlier. You can include it in 2019.2 onwards by including it like you would a regular IP repository. This thread has all that information.

Best regards,
AndrewHolzer
 

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On 5/11/2021 at 5:59 PM, AndrewHolzer said:

Hello @CurtisNotestine,

What version of Vivado are you using? Xilinx no longer includes, and has no plans for replacing the Ethernet PHY MII to Reduced MII (MII2RMII) in versions 2019.2 or later. The current work around is to obtain a copy of the IP provided in Vivado 2019.1 or earlier. You can include it in 2019.2 onwards by including it like you would a regular IP repository. This thread has all that information.

Best regards,
AndrewHolzer
 

Andrew, thank you for your reply.

I am using Vivado 2020.1. I'll try your suggestion to use 2019.1 or earlier.

Curtis

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The old guide for getting a Microblaze server running on the Nexys 4 DDR (referenced above by JColvin) mostly works for getting the Ethernet to work on the Nexys board. If you follow it straight up, the network connection to your host machine (in my case a  Windows 10 Laptop) is spotty and the connection quickly reverts to "Network cable unplugged". The Nexys A7 Reference Manual makes a note of how to fix this in section "4 Ethernet Phy". That is generate the "mii_to_rmii core" clock and the PHY clock separately in "clk_wiz_1". My clock settings are attached. "clk_out3" goes to the "mii_to_rmii core" and "clk_out4" goes to the external PHY clock pin "eth_ref_clk". Doing this makes the connection stable.

However I am still not able to get Tera Term to connect to the echo server. I am using Vivado 2019.2 and Vitis 2019.2. I pulled the source code for the "mii_to_rmii core" from Vivado 2019.1 and set it up in an IP repository reference by 2019.2. When the echo servo starts I get messages on the COM port. In my case a separate Tera Term window connected to serial port COM6. See attached. Note I have modified the default IP address in the  echo servo code. My regular internet connection was already using 192.168.1.xxx. I set up fixed IP on an unused Ethernet port on my laptop at 192.168.10.100.

Connection via TCP/IP on Tera Term fails with "Connection timed out". Any thoughs on what to try nex t appreciated.

 

Glen

 

 

 

clk_wiz_1_settings.png

tera_term_com6.png

tera_term_telnet.png

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Hi @Glen F,

I'll test this again with 2019.2; I haven't gotten to thoroughly compare your settings with what I've tried in the past (I'll likely spin up a new project unless I happen to find an old one that works), though I did notice that you set your laptop IP to be the same as the Gateway IP address that the Ethernet/microblaze demo presumes, so I don't know if that is affecting your connectivity or not.

Thanks,
JColvin

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