How to connect two FPGA boards?

[Evocati]

I am working on a project that requires 2 FPGAs, one to be used as source, the other as sink, there are some low speed signals (less than 1Mhz) to be transferred between 2 boards.

Is there any way to connect 2 FPGA boards? Which board/peripheral is needed? 

 

Thanks,

Evo

[zygot]

I've done this many times. What boards are your using?

Tips:

• make sure that you have a good bonding of the GND reference for both boards, especially for single-ended signals. PMODs have 2 GND pins.
• Don't connect any power rail of both boards together
• Before configuring both boards as a connected system take extra precautions to be sure that your have assigned the pin locations correctly; that is check the post route pin assignments. Make sure that there is no possibility of contention. The pin on the sink side should be an input only and the pin on the source side should be an output only.
• For relatively slow signalling assign output driver SLEW as slow and output drive at 4 mA or the minimum available for the first test.
• Open-drain or open collector outputs are one way to connect drivers safely.
• The safest way to connect external hardware is through external buffers as a protection for the FPGA pins.
• Before powering anything double or triple check the interface wiring and design.
• Be aware that the PMODs are not keyed... so it is possible to have connection/cabling issues with potentially disastrous consequences.   You don't want to tie the GND and VCC together or drive output buffers into either of those rails.

What exactly are your concerns?

Edited April 13, 2021 by zygot

[zygot]

I thought of something that I forgot to mention.

The standard PMODs are good for low toggling rate interfaces. Also they have 200 ohm series resistors that, to some extent, help protect from ESD and shorts, both temporary and long term, and to a lesser extent transmission line issues. Even still try and keep cabling as short as possible, especially with flying leads.

[Evocati]

Thanks for the suggestion! I thought PMOD is only used for peripherals like sensors, LED, etc, didn't know we can use them to connect boards.

So I only need a PMOD cable to connect 2 FPGA boards like this, correct?

         FPGA board 1   -- PMOD cable  -- FPGA board2

I have Zybo, Basys 3 and Nexys 4, all 3 boards have PMOD interface.

 

And is there any IPs needed inside FPGA to be used as RX/TX to drive the PMOD?

 

Thanks,

Evo

[zygot]

3 hours ago, Evocati said:

So I only need a PMOD cable to connect 2 FPGA boards like this, correct?

Well, no. A 12-pin or even 6-pin PMOD cable would violate the 2nd tip: Don't connect Vcc rails between boards. They are fine for PMODs because the add-on boards need Vcc. It's very easy to create big problems with cabling; you have to verify that the cabling is connecting the proper pins together, and nothing else. For 1 MHz signals it's probably ok to use flying leads. You can buy 6" leads with female-female headers, male-female headers or male-male headers from places like Adafruit. You want male-male wires. To be safe you might stick both ends of a male-male lead into each of the mating PMOD connectors; that is connect pins 6 and 12 together for each PMOD. That way you won't accidentally make contact with the Vcc pins with your cabling. The best way to do this is to make a custom cable. Since the PMODs are not keyed it's pretty easy to get things wrong. Verify connectivity with an ohmmeter before powering anything. Never connect or disconnect inter-board cabling while either boards is powered on.

3 hours ago, Evocati said:

is there any IPs needed inside FPGA to be used as RX/TX to drive the PMOD?

I use the HDL design flow so I just need to declare a signal as in, out or inout on the toplevel port declaration. The best way to handle external signals is to instantiate the appropriate buffer in the toplevel entity using a primitive.  If you don't do this the tools will automatically instantiate one for you, as long as your constraints file has the same name as the toplevel port declaration. If you are using the board design flow you can just make a signal external and the tools will instantiate a buffer. If you want a particular buffer type then you need to instantiate it in your design. Frankly, I don't use the board design flow, except for ZYNQ designs and my toplevel module or entity is always a VHDL or Verilog source file.. so I've never tried selecting a buffer from the IP catalog.

As preparation, make sure that you read the Series 7 Select IO User Guide. There is also a guide for instantiating primitives in HDL, I think that it's UG768.

Once you start doing designs that don't use the limited Xilinx IP or Digilent PMOD IP you are much better off using the HDL design flow. This not only gives you more control over your design but forces you to think about the details.

 

Edited April 15, 2021 by zygot

[Evocati]

Thank you Zygot for the suggestions! I have tried pmod with jumper wires, it is easier to use than I expected.

I just need to uncomment the ports from .xdc then use it just like regular input/output. And each of the 8 pins of one pmod connector can be use individually.

 

Evo

[Tim Kim]

Hi, one question.

How do the FPGA stay synched when communicating via PMOD pins?

[zygot]

6 hours ago, Tim Kim said:

How do the FPGA stay synched when communicating via PMOD pins?

Without a context "synched" has no meaning. This thread is simply about passing information between two FPGA devices on two different boards. There are a lot of use cases where this is nice if one board has hardware resources or interfaces that the other doesn't. I don't know of any FPGA devices that have the capability of being bonded or "synched" into a larger virtual device.

A simple way to do this would involve two pins and a UART in the design of each FPGA board. This is completely asynchronous so no clock-capable pins are needed. When connecting anything to an FPGA pins you have to be very careful not to drive the connection on both ends at the same time. There are plenty of steps one can take to minimize the risk of this happening... but mistakes do happen and this is one that has the potential of ruining your board. For a UART you might only need a Tx output and a Rx input. Obviously, connecting the two Tx pins is a very very bad and dangerous idea. Connecting the two Rx pins is just a dumb idea with no purpose.

For advanced level designs, an Ethernet PHY is ideal as the PHYs usually have auto-crossover capability to prevent driver contention. Just plug a cable between the two RJ-45 jacks.

As for the concept of scope in data validity, well that's where the fun happens as it's handled by design... whatever that happens to mean in the context of a particular design.

Connecting FPGA pins to external things with current sourcing capabilities requires great care. If you have obsessive tendencies this is a time where it's a benefit. If you don't, then you better learn how to emulate the condition by having a check list and being methodical about checking off the items on the list before applying power to your EVM(s). This is what eveyone who flies a plane does before every flight.

Edited September 7, 2022 by zygot