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Efficient way of reading EMIO pins and store the result into text file in SD card


Varad

Question

Respected Team,
I am using ZC702 Board in my project.  I have connected the Output of my RF front end EMIO pins. RF front end giving me output (ADC samples) at 30MHz.  I have connected the Output of RF front end to PL using EMIO. I have used PMOD JA on ZC702 board to connect the output of RF front end. Then I have configured EMIO pins as (54,55,56,57.58) as external pins.  Then I tried to read the value of pin using GPIO drivers in Xilinix SDK. 
 

My task is to collect read the samples from RF front end and write the data into text file and store it in SD card.  Right now I have written code in Xilinx SDK using available drivers. In that I am reading the EMIO pins for 1 sec and writing a data to CSV file. (Please find attached code)
 

Question:
1. As I mentioned earlier, sampling frequency of ADC in the RF front end is 30MHz. So is it possible that I can accurately read 30M samples in one seconds using the code I have written. Because when I checked using my code, I could get 0.75 Million samples in 1 sec. I have used count variable in the code which will give me last count of sample when it is coming out of while loop where I am reading the EMIO pins. So when I print the value of count then value is around 

2. Also what could be the efficient way to read the huge data and store it to SD card. 

It would be very kind of you if you could point out the errors in the code, and provide the answers to my questions. It would be great help to me.

Thanks

test.txt

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It's not clear from your description exactly how your HW interface is supposed to work because it's not clear how the external "RF Front-end" signalling is defined.

Connecting ZYNQ ARM GPIO to external signals and polling the states asynchronously is not, in general, a good way to capture data. A better way would be to implement an interface in HDL in your PL design and then transfer the results to the ARM cores through one of the AXI busses.

Using the SDK GPIO drivers will not achieve the maximum possible data throughput.

 

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Respected Zygot,


Thank you very much for your answer. 
I am really sorry about not providing the information very clearly.  Here is the detailed explanation on the Interface.  
RF front end  gives 4 bit digital data(ADC output). Sampling frequency of ADC is 30MHz. Output of  RF front end is connected to PMOD JA on ZedBoard.  In my HDL design I am using EMIO pins to connect my RF front end output to PL.  Detailed steps are as following.

1. Enable GPIO EMIO from peripheral I/O Pins

 

image.png.586ffeede6b75686ffc731939c35c458.png

2.  Make the GPIO to"External" interface

 

image.png.9dbec981bf25d4535731c45e90997679.png

 

3.  Added the constraints  in the constraint  file.

image.thumb.png.f3679b208243c8157fadd6146de842c9.png

 

image.png.80bc19699e9ec59346614e2b09171734.png

4. Generate the Bit Stream and export the hardware.

5. Use GPIO drivers in Xilinx SDK to read GPIO pins and write the results to CSV files.

 

I hope this is clear description of my interface from RF front end to ZedBoard. 

Also, I look for the suggestion you mentioned in your comment and try to do like that. And in case I stuckeed at some point I will ask here again. 

Once again thank you very much for helping.

image.png

image.png

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Respected Zygot,
 

RF front end is providing 4 bit I and Q samples. Basically down converting the received data from receiver and convert analog data to digital. So every analog value is converted to 4 bit digital value. 
So my task is to connect the 4 pins to Zedboard read the signal and store it to SD card. My only constraint is Data is sampling at 30MHz. So  I will be having 30M samples every seconds. I have to  read the sampled data on ZedBoard and store it to SD card. 

You have mentioned about AXI interface. It would  be very kind of you if you could provide some reference documents/ code. 

Thanks for helping me!!

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46 minutes ago, Varad said:

RF front end is providing 4 bit I and Q samples.

Well, that's a bit more information. You've exported 5 ARM EMIO pins and have 4-bit data. So, how do you know when the data is I or Q .. or even valid? How are you intending to synchronize your data? Polling GPIO pins asynchronously in software is not a good approach. If you implement an interface in the PL you still need to have some way to identify a point between the changing data signal transitions to sample the signals at a valid state. Usually this is done in a source synchronous manner with the data source supplying a clock reference.

There seems to me to be a lot of conceptual details missing in your approach. You don't anticipate the need for some sort of temporary data storage? You seem to be expecting that the ARM core will be doing nothing except sampling your GPIO pins without interruption and be able to write to a FLASH memory directly. Does this seems like a good idea to you?

The ZYNQ device is an FPGA... that happens to have a hard ARM core complex available for support.

Edited by zygot
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Respected  Zygot,
Yes you are right.I need clock reference from data source. As mentioned earlier I have 5 ARM EMIO pins , amongst them 4 are data pins and remaining pin is clock pin. The clock frequency is same as ADC sampling frequency. So in order to validate my data I need to  store the data only when I detect the rising edge of clock signal?
In the second question, yes my current approach is not good. I thought of implementing a buffer, and I will store it in  uffer till it gets full. When it is full then I will write this data to SD card. But I thought there could be one issue. I could loose some data . This is because everytime buffer gets full I will write it to Sd card and empty the buffer. So in this process I could loose some sample points.
I am also thinking that I am missing something conceptually. Could you please suggest me a better approach for this task please. Also if you have some reference documents related to this could you please share it with me.

Thanks and regards!!

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3 hours ago, Varad said:

The clock frequency is same as ADC sampling frequency. So in order to validate my data I need to  store the data only when I detect the rising edge of clock signal?

"?" Indeed. I don't know which edge, or if both edges, produce data output. You need to know this. Additionally, you still haven't indicated how you expect to differentiate I and Q data. I'm not sure how you thought that polling GPIO pins from an ARM core was going to work.

On 4/7/2021 at 10:12 PM, Varad said:

I have used PMOD JA on ZC702 board to connect the output of RF front end.

That's interesting because my schematic of the ZC702 doesn't show a JA PMOD. In fact that only PMOD type header isn't even configured as one of the Digilent standard or differential PMOD types. Digilent rates its standard type PMOD as appropriate for 10 MHz signalling maximum by the way.

It wouldn't be appropriate for me to do your work for you even if I had sufficient information to do it. I suggest spending some time reading the pertinent Xilinx literature on the ZYNQ device on your hardware platform, looking through some of the XIlinx AXI IP user guides and of course the ZC702 schemtic and user guide material. It wouldn't hurt to have an understanding of how your RF Front end interface works either. Trying to implement a design approach without understanding how your hardware and development tools work is very unlikely to produce acceptable results.

Edited by zygot
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Respected Zygot,
4 pins I have mentioned earlier are as following :

I0,I1 (I value) , Q0,Q1(Q value). I thought of connecting them to GPIO pins and reading the values will work. My approach was as following:

connect I0 to GPIO0[0]

connect I1 to GPIO[1]

connect Q0 to GPIO[2]

connect Q1 to GPIO[3]

Connect ClockOut (RF front end) to GPIO[4].

Then reading GPIO pin value and storing them in the file.  
 

Could you lease tell me if my approach is correct or not. If I am not clearer with approach or I am missing technical understanding could you please tell where should I focus more.

Thanks.

RF front end is providing 4 bit I and Q samples. Basically down converting the received data from receiver and convert analog data to digital. So every analog value is converted to 4 bit digital value. 
So my task is to connect the 4 pins to Zedboard read the signal and store it to SD card. My only constraint is Data is sampling at 30MHz. So  I will be having 30M samples every seconds. I have to  read the sampled data on ZedBoard and store it to SD card. 

You have mentioned about AXI interface. It would  be very kind of you if you could provide some reference documents/ code. 

Thanks for helping me!!

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So now you're using the Zedboard... Ok, so your connection scheme implies that what you are connecting to is supplying DDR data; 2 bits per clock edge = 4-bit data per clock cycle. That's an unusual format for supplying complex data samples. JA on the Zedboard is a slow standard PMOD but at least 2 pins are connected to FPGA SRCC pins, so that's in your favor. Capturing DDR data at a 30 MHz clock rate on a standard PMOD is highly doubtful. Regardless, you will have to assemble the DDR data into 4-bit data samples before sending the IQ data to storage.

Based on the information that you've provided I believe that I've given as much help as I can. As to using AXI IP for transferring data from the PL to the PS or PS controlled external memory that's part of your task to see what IP Xilinx has to offer and choose what's preferable for your project. There are IP guides available through the Document Navigator installed with the tools.  Though there are AXI IP that can DMA data directly from the PL into the PS controlled DDR memory, trying to do that for ~30 MB of contiguous data is not for beginners. Also, most Xilinx IP comes with an example project that demonstrates at least one way to use the IP. It gets into your project when you generate the IP. If you don't have any idea what IP is available for your HW platform you can see a list in VIvado from the IP catalog while making your board design.

Student projects get into trouble because the design process is usually out of order. First a hardware platform is chosen based on cost. Then a wild guess as to how parts of the design concept might be implemented is thrown out and everyone goes off on their own and hopes that they can figure out how to make that plan work. Then after a few experiments the problems pop up and then the panic sets in. Engineering is cruel to the under prepared...

Edited by zygot
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