Ceonceptual question: PL triggered DMA transfer to on chip memory in the Zynq

[james_h_66 0]

Hello All,

In the DMA interrupt examples (Xilinx has one that I'm using), the DMA transfer interrupts, and inside the interrupt routine, the processor calls [for example] the "XAxiCdma_SimpleTransfer" function to transfer the data from source (some memory in the PL) to destination (the PS memory). 

--> I'm looking for a way that the DMA transfer happens automatically, BEFORE the interrupt is called.  That is, when the processor interrupt is triggered, the values have already been transferred from PL to the PS side.  This would reduce processor wait time, so that the PS doesn't need to call the "XAxiCdma_SimpleTransfer" inside the interrupt.

I think this is the idea of making the PL side as an "AXI master", but I'm not certain.  Is there an example of doing the above?

[zygot 231]

20 hours ago, james_h_66 said:

I think this is the idea of making the PL side as an "AXI master",

There are two general ways to DMA data from the PL into PS controlled external memory that I am familiar with.

You can use the PS-PL AXI interconnect and implement the DMA in your PL design. Xilinx has a number of AXI IP that does this, or you can write your own IP. Not all PS-PL AXI interconnect paths allow the PL to be the AXI master. You can also select AXI IP that lets the PL design be the bus slave. Which kind of AXI interconnect you choose might be driven by HW or SW considerations.

You can also use the ARM core DMA controller to transfer data.

However you do DMA from the PL the design starts with the HW design, not selecting available SDK DMA example projects.

If you want to have your PL design automatically DMA data into PS controlled external memory without software intervention I think that you will need to implement some sort of AXI master in your HW design. You will have to read through the IP user guides for each AXI master IP under consideration to understand how they work if using Xilinx IP. There are a number of ways that your PL design could cause an interrupt for your ARM cores after data transfer has completed.

Edited Thursday at 02:07 PM by zygot