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About daisy Chaining the I2C Pmod


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Previously, in this forum, I knew that I can use daisy chain method to allow my PMOD HYGRO and PMOD AQS to be connected into the same port. I started with my new vivado block design. Since I don't have much knowledge about IIC parallel communication, when I transfer my block design file to Vitis IDE, it doesn't show the data from PMOD HYGRO. I want to know if any part of my block design and C code in the Vitis wrong. 

Also, can anyone tell me how the I2C parallel communication transfer works? Thanks

image.thumb.png.31d90e82c1cbc8b915851ecda57cdc1b.png

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Hi @helloworld1029,

I'm not sure that Digilent has any examples for daisy-chaining I2C Pmods together in Vivado/Vitis/SDK. The forum post you are referring to is for putting two Pmods on the same port, but one 6-pin Pmod uses the top half of the Pmod host port and the other Pmod uses the bottom half of the Pmod host port, which is not daisy chaining.

I haven't attempted to create such a design, but this won't be easy to accomplish in the block design portion and have everything get properly ported over to Vitis. The reason for this is that with daisy chaining, you'll effectively be having the two Pmod IPs attempting to place their IO buffers and scripted constraints on the same pins, which Vivado will (wisely) complain about and not let you do. Using a more general AXI I2C controller rather than a Pmod IP may also be a wiser option in terms of accounting for both Pmods on the software side in Vitis/SDK.

I would probably attempt two different methods. One would be to leave out the daisy-chained Pmod entirely from the block design to avoid having to fight with Vivado/Vitis to get it "properly" ported over to Vitis and only have the first I2C module in the block design. You could then account for other modules in the daisy chain on the software side through other helper functions.
The other would be have both blocks in the design, much like you have done in your screenshot since both should get imported in the hardware platform/.xsa to the Xilinx software tool appropriate to whatever version you are using. It'll then be much easier to adjust or copy over as appropriate the existing libraries/functions so that they both work on the I2C module that the Xilinx tools think is directly connected to the Pmod port. I'd probably do this by porting over the further downstream Pmod library functions into the libraries of the directly connected module, and then adjusting the main.c function as appropriate to talk to the different modules as the design requires.

To be clear, there are multiple approaches that could be taken to this particular design; but all of them will require different amounts of finagling in the Xilinx tools to make the design work.

Thanks,
JColvin

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@JColvinRegarding to two solutions, I would like to clarify somethings. First, for the first solution, if I only leave the AXI IIC inside the block design, how should I connect to port JC ( I tried in my way, u can see in the pic below). Also, where can I find the resource on how to write the C or Cpp code for the i2c communication between the AXI IIC , HYGRO and AQS? For second solution, I don't fully understand your explanation. If not wrong, you mean that I don't use the AXI IIC and use two Pmod IP Core instead.  I am not sure that I connect one of the Pmod into connector JC, or I do not connect to any port in Vivado Block Design, and specifying the connection of port through write C code in Vitis IDE. I am just not so sure. 

And could you further explain this portion, I really don't quite understand that. 

"It'll then be much easier to adjust or copy over as appropriate the existing libraries/functions so that they both work on the I2C module that the Xilinx tools think is directly connected to the Pmod port. I'd probably do this by porting over the further downstream Pmod library functions into the libraries of the directly connected module, and then adjusting the main.c function as appropriate to talk to the different modules as the design requires."

Here is the block designs I did based on my understanding of your comment. I connect the IIC of the AXI IIC to custom. And change the variable name in JC port. image.thumb.png.759c03cac11e8728c739c0193fa42247.pngimage.thumb.png.6c11d2927db7cef2a41cf93154a2180f.png

In addition, I have tired with the connection between one port  and one Pmod and run my program  in my ZYbo z720 with the help of demo code. 

 

Thanks

helloworld1029

Edited by helloworld1029
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