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Create a Variable Duty Cycle using VHDL



How to generate a variable duty cycle from this code? This code is for 10% duty cycle, 500 Hz frequency, but I want to generate 10%, 30%, 50%, 70% and 90% duty cycle. The clock frequency is 50 MHz. I want to generate a variable duty cycle from 5 variable frequency which are 500 Hz, 1 kHz, 50 kHz, 500 kHz, and 1 MHz. Please someone help me. I need your help.

Thank you.



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Welcome back Jaiko007!  

Before diving in to help, may I ask some questions?  I'm dying to know 1) what class you are taking, 2) what school you are at, 3) how you managed on your last couple of projects, and perhaps more importantly 4) what your instructor has already taught you on this one.  Is this following a lecture on the topic?  Do you have your instructor's lecture notes anywhere?  Are those helpful to you?

After that, it would really be helpful to know your instructors collaboration policy.



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Edge triggered D flip flops once you set up a counter to maintain the desired frequency setpoints.

Asynchronous inputs required to tag the desired Fr output to the next register.

If it a Synchronous input then loop CLR at the desired MSB.

Hope this helps a bit, Are you using Altera or Spice? hmmmm 

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